A Spatial Array for Spectrally Agile Wireless Processing

TL;DR

The paper tackles the need for scalable, spectrally agile hardware in Massive MIMO base stations. It introduces a reconfigurable spatial array, a flexible systolic-like compute unit designed to support a broad class of wireless kernels including filtering, convolution, matrix operations, and spectrum sensing tasks. The authors synthesize both the spatial array and specialized HLS cores in a 32 nm process and compare latencies, throughputs, area, and power under identical memory bandwidth constraints. Results show the spatial array approaches the efficiency of specialized cores for many kernels, notably excelling in matrix-matrix multiplication, while preserving reconfigurability; the study highlights the trade-offs between area, power, and compute throughput that shape agile, scalable wireless hardware.

Abstract

Massive MIMO is a cornerstone of next-generation wireless communication, offering significant gains in capacity, reliability, and energy efficiency. However, to meet emerging demands such as high-frequency operation, wide bandwidths, co-existence, integrated sensing, and resilience to dynamic interference, future systems must exhibit both scalability and spectral agility. These requirements place increasing pressure on the underlying processing hardware to be both efficient and reconfigurable. This paper proposes a custom-designed spatial array architecture that serves as a reconfigurable, general-purpose core optimized for a class of wireless kernels that commonly arise in diverse communications and sensing tasks. The proposed spatial array is evaluated against specialized cores for each kernel using High-Level Synthesis (HLS). Both the reconfigurable and specialized designs are synthesized in a 32 nm process to assess latency, throughput, area, and power in realistic processes. The results identify conditions under which general-purpose systolic architectures can approach the efficiency of specialized cores, thereby paving the way toward more scalable and agile systems.

Figures (5)

• Figure 1: The architectural design of the proposed spatial array is depicted. The illustration on the left presents our $8 \times 8$ array, demonstrating SRAM connections accessible from the upper, lower, and lateral sides of the array, facilitating adaptable data injection under various conditions. The illustration on the right provides an in-depth representation of the architecture of our processing element.
• Figure 2: Number of multipliers, Area ($mm^2$), (c) Power consumption ($mW$) for each kernel in the proposed Spatial Array compared with the implementations.
• Figure 3: Latency, Throughput, Performance per area ($Gops/s/mm^2$), Performance per power ($Gops/s/mW$) for each kernel in the proposed Spatial Array compared with the implementations.
• Figure 4: Radar charts illustrating normalized latency, inverse throughput, area, and power consumption for the proposed spatial array compared with implementations for five benchmark kernels from left to right: matrix–matrix multiplication, matrix–vector multiplication, outer product, FIR filtering, and vector magnitude squared.
• Figure 5: Radar charts depicting normalized latency, inverse throughput, area, and power consumption for the proposed spatial array versus implementations provisioned with 4, 16, and 64 multipliers across two benchmark kernels from left to right: matrix–matrix multiplication and vector magnitude squared.