Exploiting Movable Logical Qubits for Lattice Surgery Compilation

TL;DR

The paper tackles the high schedule-depth overhead of lattice-surgery-based quantum computation by enabling movable logical qubits through teleportation during CNOT operations. It develops a color-code focused, proof-of-concept compilation scheme and a practical heuristic pipeline (sliding window, simulated annealing, shortest-first routing) that dynamically repositions logical data qubits to minimize routed depth. Numerical results show significant depth reductions compared to traditional static-mapping approaches, identifying regimes where the method is especially beneficial and demonstrating applicability to superconducting hardware as well as other architectures. An open-source implementation is provided to facilitate adoption and further development.

Abstract

Lattice surgery with two-dimensional quantum error correcting codes is among the leading schemes for fault-tolerant quantum computation, motivated by superconducting hardware architectures. In conventional lattice surgery compilation schemes, logical circuits are compiled following a place-and-route paradigm, where logical qubits remain statically fixed in space throughout the computation. In this work, we introduce a paradigm shift by exploiting movable logical qubits via teleportation during the logical lattice surgery CNOT gate. Focusing on lattice surgery with the color code, we propose a proof-of-concept compilation scheme that leverages this capability. Numerical simulations show that the proposed approach can substantially reduce the routed circuit depth compared to standard place-and-route compilation techniques. Our results demonstrate that optimizations based on movable logical qubits are not limited to architectures with physically movable qubits, such as neutral atoms or trapped ions - they are also readily applicable to superconducting quantum hardware. An open-source implementation of our method is available on GitHub https://github.com/munich-quantum-toolkit/qecc.

Figures (6)

• Figure 1: Overview of the movable logical qubits approach. (a) A color code patch encodes a single logical qubit which can be used as either a logical data or ancilla patch. (b) Macroscopic routing graph $\mathcal{R}$; black and white nodes represent data and ancilla patches, respectively. Paths in blue indicate standard CNOT gates performed via lattice surgery with the measurement-based scheme shown in (c); the pink tree depicts a CNOT with teleportation as shown in (d). The example displays that the target qubit with label 3 is teleported to the position marked by a pink star. (e, f) display the data and ancilla patches as 1D linearized view of the routed layers. (f) shows the future routed layers that determine the teleportation-based movements in (e).
• Figure 2: (a) CNOT + teleportation of control to ancilla. $\alpha, \beta, \gamma \in \{0, 1\}$ denote the measurement outcomes of the corresponding Pauli measurements. (b) Possible teleportation on the geometry with the color code on the microscopic level. The $X_LX_L$ and $Z_LZ_L$ measurements are performed along the violet and orange dashed lines, respectively.
• Figure 3: Derivation of CNOT + teleportation from control to ancilla with ZX calculus. Z-spiders are depicted in white and X-spiders in grey. (a) Representation of $ZZ$ measurement as quantum circuit and corresponding ZX diagram. (b) Translation of circuit in \ref{['fig:cnotmove_a']} into ZX diagrams. The applied ZX rules per step are displayed in pink following wetering_zx-calculus_2020. The final expression is topologically equivalent to the CNOT gate in ZX calculus.
• Figure 4: CNOT + teleportation at the macroscopic level. (a) Routing of the given circuit with four CNOT gates and two logical layers leads to three routed layers if the choice of qubit mapping is static. (b) With a suitable choice of a CNOT + teleportation one can route the logical circuit in two routed layers.
• Figure 5: Heuristic optimization of routed depth with CNOT + teleportation. Top: The logical circuit is split in logical layers (separated by dashed lines), with the first enclosed by an orange box. Bottom: Logical circuit compilation into routed layers. First, the CNOTs of the first logical layer are routed in the standard way as indicated in blue (i). Then, based on the next $k$ logical layers, tree structures (pink) are searched that minimize the number of routed layers $\widetilde{\ell}$ (ii). Afterwards (iii), the $\widetilde{\ell}$ resulting routed layers are fixed in the schedule. The procedure is repeated with the next logical layer (i).

Theorems & Definitions (3)

• Example 1
• Example 2
• Example 3