A CMOS+X Spiking Neuron With On-Chip Machine Learning

TL;DR

The paper addresses the design of energy-efficient edge-oriented neuromorphic hardware by integrating MTJ-based spintronics with CMOS in a CMOS+X framework to realize spiking neurons capable of on-chip learning. It introduces an NMOS+MTJ neuron whose magnetization dynamics drive neuron-like spiking without extra control circuitry, and demonstrates fully analog, spike-time gradient-descent learning for a multilayer network in LTspice. The authors validate end-to-end supervised learning on a nonlinear XOR task entirely in analog hardware, achieving convergence through spike-timing updates without digital processing. This work outlines a practical path toward compact, low-power, in-memory neuromorphic processors using MTJ-enabled spiking neurons for edge AI.

Abstract

We present the design and numerical simulation of a spiking neuron capable of on-chip machine learning. Built within the CMOS+X framework, the spiking neuron consists of an NMOS transistor combined with a magnetic tunnel junction (MTJ). This NMOS+MTJ unit, when simulated in the industry-standard circuit simulation software LTspice, reproduces multiple functions of a biological neuron, including threshold spiking, latency, refractory periods, synaptic integration, inhibition, and adaptation. These behaviors arise from the intrinsic magnetization dynamics of the MTJ and do not require any additional control circuitry. By interconnecting the NMOS+MTJ neurons, we construct a model of an analog multilayer network that learns through spike-timing-dependent weight updates derived from a gradient-descent rule, with both training and inference modeled in the analog domain. The simulated CMOS+X network achieves reliable spike propagation and successful training on a nonlinear task, indicating a feasible path toward compact, low-power, in-memory neuromorphic hardware for edge applications.

Figures (7)

• Figure 1: (a) MTJ structure showing the reference layer $\mathbf{p}_1$, the analyzer layer $\mathbf{p}_2$, and the free layer $\mathbf{m}$ whose magnetization can rotate in the $xy$-plane. The resistance $R_{\mathrm{MTJ}}(\phi)$ depends on the angle between $\mathbf{m}$ and $\mathbf{p}_2$. (b) NMOS+MTJ neuron circuit in which a magnetic tunnel junction is connected in series with an NMOS transistor. The input voltage $V_{\mathrm{in}}$ is applied to the transistor gate, and the output voltage $V_{\mathrm{out}}$ is measured at the drain. The series connection ensures that the same current $I_{\mathrm{MTJ}}$ equals the drain current $I_D$ and flows through both elements.
• Figure 2: Simulation results of the NMOS+MTJ neuron circuit in LTspice. (a) Input gate voltage $V_{\mathrm{in}}$. (b) Corresponding drain current $I_D$. (c) Free layer magnetization angle $\phi$. (d) Time-dependent MTJ resistance $R_{\mathrm{MTJ}}$. (e) Output voltage $V_{\mathrm{out}}$.
• Figure 3: Biological neuron-like behaviors reproduced by the NMOS+MTJ neuron circuit. In the plot, the red curve shows the input voltage and the blue curve shows the output voltage. (a) Leaky integrate and fire / synaptic integration: multiple subthreshold inputs combine over time to trigger a spike. (b) Refractory period: demonstrates absolute and relative refraction following an initial spike. (c) Inhibition: an inhibitory signal prevents spiking that would otherwise occur. (d) Frequency modulation: constant input above threshold produces a spike train whose frequency depends on input amplitude. (e) Adaptation: response latency changes due to a shift in input bias, even with identical stimulus pulses.
• Figure 4: Signal propagation in a chain of NMOS+MTJ neurons with tunable synapses. (a) Diagram of a three-neuron chain, where circles represent neurons and arrows represent synapses. (b) Electrical schematic of the NMOS+MTJ neuron chain, with each synapse implemented as a tunable voltage amplifier. (c) Output voltage waveforms from neuron 1 (orange), neuron 2 (blue), and neuron 3 (green). (d) Corresponding synapse outputs, showing the amplifier signals at their respective applied synaptic weights. (e) Response latency as a function of synaptic weight, where synaptic weight is expressed as an absolute value.
• Figure 5: Architecture of the NMOS+MTJ neural network for XOR classification. (a) Network diagram with encoding neurons ($A$, $B$), input-layer neurons ($i_1$, $i_2$), and output neuron ($o_1$), and synaptic weights. (b) XOR truth table with bias input and target output for each input combination.