Modelling the Impact of Device Imperfections on Electron Shuttling in SiMOS devices

TL;DR

This work addresses robust conveyor-belt electron shuttling in SiMOS devices by performing full 3D Poisson–Schrödinger simulations that incorporate oxide-interface roughness, gate fabrication imperfections, and charge traps. The authors demonstrate a low-confinement transition to bucket-brigade due to multi-layer gate screening, which can be reversed by raising the confinement to $V_c\gtrsim150$ mV, while interface roughness and misalignment generally preserve high fidelity transport with negligible loss. Positive interface defects emerge as the principal obstacle, capable of trapping or strongly perturbing the shuttle, whereas negative defects mainly deform the wavefunction without causing loss at practical voltages; hydrogen passivation strategies are suggested to mitigate trap densities. The results establish operating guidelines for reliable charge transport in SiMOS architectures and provide a scalable modeling framework to extend to spin, valley, and phonon-relaxation effects for quantum information transfer.

Abstract

Extensive theoretical and experimental work has established high-fidelity electron shuttling in Si/SiGe systems, whereas demonstrations in Si/SiO2 (SiMOS) remain at an early stage. To help address this, we perform full 3D simulations of conveyor-belt charge shuttling in a realistic SiMOS device, building on earlier 2D modelling. We solve the Poisson and time-dependent Schrodinger equations for varying shuttling speeds and gate voltages, focusing on potential pitfalls of typical SiMOS devices such as oxide-interface roughness, gate fabrication imperfections, and charge defects along the transport path. The simulations reveal that for low clavier-gate voltages, the additional oxide screening in multi-layer gate architectures causes conveyor-belt shuttling to collapse to the bucket-brigade mode, inducing considerable orbital excitation in the process. Increasing the confinement restores conveyor-belt operation, which we find to be robust against interface roughness, gate misalignment, and charge defects buried in the oxide. However, our results indicate that defects located at the Si/SiO2-interface can induce considerable orbital excitation. For lower conveyor gate biases, positive defects in the transport channel can even capture passing electrons. Hence we identify key challenges and find operating regimes for reliable charge transport in SiMOS architectures.

Figures (15)

• Figure 1: (a) Schematic of a typical quantum dot array structure used for shuttling with clavier-gates connected in ABCDABCD configuration. Figure modified from jeon2025robustness. (b) Bucket-brigade shuttling transfers the electron wavefunction between adjacent QDs through a series of adiabatic Landau-Zener transitions that tip the particle from one dot to the next. (c) Conveyor-belt shuttling creates a smoothly travelling potential minimum by applying phase-shifted sinusoidal voltages to adjacent electrodes, continuously transporting the electron along the array. (d) Example phase-shifted voltage pulses applied to clavier-gates for $V_c=500$ mV and shuttling speed $v=50$ m/s, which corresponds to a frequency of 357 MHz for the 4-gate unit cell with period $d=140\text{ nm}$ shown in (e). (e) Cross-section of the simulated shuttling device, with its clavier-gates in ABCDABCD configuration. The layer 1 confinement gates ('side-gates') are separated from the Si/SiO$_2$ interface in the z-direction by 15 nm of oxide, and each layer has 5 nm of oxide deposited between them. The electrostatic potential is solved for the entire device and plotted here with contours. The Schrödinger evolution occurs in a smaller quantum region in the channel, shaded in gray.
• Figure 2: (a) The orbital ground state infidelity at the end of the shuttling down the channel for different clavier-gate voltages and shuttling speeds, with the side-gate voltage fixed at $V_s=-1500\text{ mV}$. A diverging colourmap centered on a ground state fidelity of 99% ($1-\mathcal{F}=10^{-2}$) indicates where shuttling becomes adiabatic. (b) Mean position of electrons shuttled at 20m/s along a flat interface for different clavier-gate voltages with $V_s=-1500\text{ mV}$. At $V_c=100\text{ mV}$ the confinement under layer 3 gates is very weak due to additional screening and the conveyor minimum effectively jumps from under gate C to under gate A, causing orbital excitations.
• Figure 3: Snapshots from 3D simulations of shuttling 20 m/s along a flat interface with $V_c=100\text{ mV}$ and $V_s=-1500\text{ mV}$. Shown are slices in the x-y plane taken 1 nm below the oxide interface of (a) the potential generated by the gates and (b) the electron wavefunction with potential contours. The shuttling direction is indicated by the red arrows, and the potentials in the plane under clavier-gates ABCD with x-positions 17.5 nm, 52.5 nm, 87.5 nm, 122.5 nm are marked in red. Successive times at $t=0$, $t=\frac{1}{4}t_{\rm max}$, $t=\frac{1}{2}t_{\rm max}$, $t=\frac{3}{4}t_{\rm max}$ where $t_{\rm max}$ is the time for one complete shuttling period of 140 nm, are displayed top to bottom. At these voltages the confinement under layer 3 gates is very weak due to additional screening, and the conveyor minimum effectively jumps from under gate C to under gate A causing orbital excitations.
• Figure 4: Interface topography of the simulated quantum region (marked in Fig. \ref{['fig: combined schematic']}e) for the RMS values used in simulations. Interfaces for $\text{RMS}=0.3,0.5,0.7,0.9\text{ nm}$ using a Hurst coefficient of $H=0.3$ are displayed top to bottom. These were generated using the ACF-PSD approach discussed in Sec. \ref{['sec: interface_roughness']}, where we model the interface using a power-law functional form for the ACF to capture the self-affine structure of the roughness.
• Figure 5: Snapshots of electron charge density from 3D simulations of shuttling an electron down the channel at 50 m/s with RMS=0.7 nm, $V_c=250\text{ mV}$ and $V_s=-1500\text{ mV}$. Shown are (a) a slice in the x-y plane taken 1 nm below the mean height of the oxide interface, and (b) a slice in the x-z plane taken at the center of the channel ($y=0\rm ~nm$). The shuttling direction is indicated by the red arrow, and contours of the potential (including the rough interface) in meV are shown in black. The thick black line corresponds to the 3eV potential step between the silicon bulk and silicon oxide layer. Successive times are shown, top to bottom. The model has periodic boundary conditions and so the electron exiting to the left in the middle frame, enters from the right in the lowest frame.