SDQC: Distributed Quantum Computing Architecture Utilizing Entangled Ion Qubit Shuttling

TL;DR

SDQC tackles the challenge of scalable fault-tolerant quantum computing on trapped-ion platforms by fusing deterministic ion shuttling with distributed entanglement distribution. The authors introduce a color-code based QEC scheme with segmented stabilizers and a superdense syndrome extraction protocol tailored for SDQC, enabled by pipelined gate teleportation to achieve scale-independent logical clocks. Through detailed modeling and simulations, SDQC demonstrates lower logical error rates and faster logical clock speeds compared with QCCD and Photonic DQC for large-scale tasks, including a $256$-bit ECDLP, while maintaining comparable space costs. The work highlights the practical potential of SDQC to enable large-scale quantum computation by combining the strengths of DQC and QCCD, with clear paths for extending to universal fault-tolerant operation and code–architecture co-optimization.

Abstract

We propose Shuttling-based Distributed Quantum Computing (SDQC), a hybrid architecture that combines the strengths of physical qubit shuttling and distributed quantum computing to enable scalable trapped-ion quantum computing. SDQC performs non-local quantum operations by distributing entangled ion qubits via deterministic shuttling, combining the high-fidelity and deterministic operations of shuttling-based architectures with the parallelism and pipelining advantages of distributed quantum computing. We present (1) a practical architecture incorporating quantum error correction (QEC), (2) pipelining strategies to exploit parallelism in entanglement distribution and measurement, and (3) a performance evaluation in terms of logical error rate and clock speed. For a 256-bit elliptic-curve discrete logarithm problem (ECDLP) instance, which requires 2,871 logical qubits at code distance 13, SDQC achieves a logical error rate which is $1.20^{+0.94}_{-0.45}\times10^{-8}$ of Photonic DQC error rate and $3.79^{+5.09}_{-2.84}\times10^{-3}$ of Quantum Charge-Coupled Device (QCCD) error rate, while providing 2.82 times faster logical clock speed than QCCD.

Figures (17)

• Figure 1: Trapped-ion QC and its scalable architectures. (a) In trapped-ion QC, ions are trapped in an electric potential well and form a Coulomb crystal that shares a motional mode. The quantum information is encoded into the electronic states of ions, which are manipulated by external fields such as lasers and microwaves and measured via state-dependent fluorescence. Two main architectures have been proposed for scaling trapped-ion quantum computing: (b) Photonic DQC and (c) QCCD. (b) In Photonic DQC, remote entanglement is generated by Bell-state measurements between photons scattered from ions located in separate modules, enabled by ion-photon interfaces. This approach provides asynchronous, modular connectivity with scale-independent distribution latency, while the probabilistic nature and low fidelity of remote entanglement generation remain key challenges. (c) QCCD architecture instead achieves scalability by directly shuttling ion qubits by dynamic control of the trapping potential. While it offers deterministic operations and high-fidelity gates, its performance is constrained by scale-dependent latency and ion loss risks during transportation. (d) SDQC integrates deterministic ion shuttling with a distributed architecture to enable non-local quantum operations with high fidelity and low latency via asynchronous and pipelined entanglement distribution.
• Figure 2: Shuttling-based distributed quantum computing (SDQC) architecture. (a) Schematic of SDQC architecture. Each unit cell consists of a processor node, an entanglement factory, and a detector. Unit cells are repeated horizontally and connected via a shuttling network. Red and blue circles represent data qubits and entangled qubit pairs for gate teleportation or syndrome extraction (see Sec. \ref{['subsection:SyndromeExtractionforErrorCorrection']}), respectively. Arrows indicate shuttling flow, and numbers correspond to the gate teleportation steps described in (b) and in the main text. (b) Inter-node two-qubit gates are implemented via the gate teleportation protocol. An entangled pair is generated and transported from the entanglement factory (Steps 1--2), and they interact with data qubits $\Psi_1$ and $\Psi_2$ individually (Step 3). After the entangled qubits are shuttled to detectors and measured (Steps 4--5), feedforwards are applied to data qubits based on the measurement result. The overall result of the protocol results in a remote CNOT between the data qubits. Since Steps 1 and 2 do not involve data qubits, their latency can be hidden through pipelining. (c) Connectivity topology of SDQC. SDQC supports two types of two-qubit gates, intra-node and inter-node gates, resulting in a layered connectivity that reflects both local and non-local interactions.
• Figure 3: Quantum error correction model. (a) Superdense color code. Each vertex hosts a data qubit, and the circles on the faces or outside the boundary indicate syndrome extraction qubits. There are two types of faces: 1) hexagonal and 2) trapezoidal. To overcome the limitation of chain capacity, we place segmented lines such as the dashed line 3), which intersect multiple faces and divide the data qubits into partitions that are located in neighboring chains. The stabilizers under the segmentation lines are referred to as segmented stabilizers. (b) Physical implementation of syndrome extraction in SDQC. The red and blue circles represent data and syndrome extraction qubits, respectively. A pair of syndrome extraction qubits for a segmented stabilizer are shuttled to different nodes, interact with data qubits, and then shuttled back to a common detector to be measured in the Bell basis. On the other hand, syndrome extraction qubits for non-segmented stabilizers are shuttled to the same node and processed within it, except for the final measurements. (c) Superdense syndrome extraction circuit. The circuit comprises Bell state preparation and distribution, entangling gates between data and syndrome extraction qubits (yellow), and Bell measurements depicted separately in (d) or (e). The upper (lower) circuit measures $X$ and $Z$ stabilizers on a hexagonal (trapezoidal) face. Grey and blue lines indicate data and syndrome extraction qubits, respectively. Wavy double lines stand for shuttling. (d), (e) Bell measurement circuits for non-segmented and segmented stabilizers. Gray layers include shuttling and the following operations in detectors.
• Figure 4: Logical qubit segmentation for various code distances. Due to the limited qubit capacity of each chain, SDQC segments the physical qubits of a logical qubit across multiple processor nodes or chains to accommodate larger code distances ($d_\mathrm{code} \geq 7$). The dashed lines indicate segmentation boundaries. The layout details are provided in Appendix \ref{['appendix:PhysicalQubitMappingforLogicalQubit']}.
• Figure 5: Pipelined execution of the FT cycle in SDQC. (a) A sequence of a single FT cycle in SDQC, including one logical CNOT gate and repeated syndrome extractions. A logical CNOT gate is implemented as transversal gates via parallel gate teleportations (Steps 1--6). Following the gate operation, syndrome extractions are repeated for $d_\textrm{code}$ rounds to perform quantum error correction (Steps 7--14). All syndromes can be extracted in parallel by leveraging intra-node gates parallelism and appropriate scheduling. Gray-colored steps indicate pipelined stages, while black-colored steps denote operations that effectively set the overall FT cycle latency. (b) Temporal diagram of the pipelined FT cycle. Entangled pair preparation of gate teleportation qubits (Steps 1--2) and syndrome qubits (Steps 7--8), as well as Bell measurement of syndrome qubits (Steps 10--11, 13-14), are hidden behind data qubit operations (Steps 3--6, 9, 12) by pipelining. Blue, orange, and red blocks represent the duration of the logical CNOT gate, QEC cycles, and Bell measurement for segmented-stabilizer, respectively. Gray arrows indicate ion shuttling operations across architectural components, where horizontal extent denotes average shuttling duration. Timing values in this diagram correspond to a code distance of $d_\textrm{code}=13$