Chiplet technology for large-scale trapped-ion quantum processors

TL;DR

This work describes the design concept of a chiplet-based trapped-ion quantum processor and demonstrates the technology with an example of an integrated individual-ion addressing system for a ten-ion crystal that emphasizes the modularity of the chiplet approach.

Abstract

Trapped ions are among the most promising platforms for realizing a large-scale quantum information processor. Current progress focuses on integrating optical and electronic components into microfabricated ion traps to allow scaling to large numbers of ion qubits. Most available fabrication strategies for such integrated processors employ monolithic integration of all processor components and rely heavily on CMOS-compatible semiconductor fabrication technologies that are not optimized for the requirements of a trapped-ion quantum processor. In this work, we present a modular approach in which the processor modules, called chiplets, have specific functions and are fabricated separately. The individual chiplets are then combined using heterogeneous integration techniques. This strategy opens up the possibility of choosing the optimal materials and fabrication technology for each of the chiplets, with a minimum amount of fabrication limitations compared to the monolithic approach. Chiplet technology furthermore enables novel processor functionalities to be added in a cost-effective, modular fashion by adding or modifying only a subset of the chiplets. We describe the design concept of a chiplet-based trapped-ion quantum processor and demonstrate the technology with an example of an integrated individual-ion addressing system for a ten-ion crystal. The addressing system emphasizes the modularity of the chiplet approach, combining a surface ion trap manufactured on a glass substrate with a silicon substrate carrying integrated waveguides and a stack of 3D-printed micro-optics, achieving diffraction-limited focal spots at the ion positions.

Figures (8)

• Figure 1: Illustration of a conceptual chiplet stack forming a SiP as platform for scalable TIQC processors. An electro-optical packaging at the bottom serves as an active interposer for the mounted ASICs and PIC chiplets in the middle layer. ASICs and PIC chiplets are laterally interfaced via the interposer and serve in turn as mounting platform for the trap chiplet and further optical elements, e.g., a focusing unit manufactured in a slotted area of the trap chiplet.
• Figure 2: Illustration of a QCCD-type TIQC processor constructed with chiplet technology introduced in Fig. \ref{['fig: chiplet_vision']}. The SiP consists of a trap chiplet bonded onto a PIC chiplet and interfaced on a electro-optical package used for the signal fan-out to peripheral system components. The chiplet stack is mounted via standardized flip-chip bonding technique onto the electro-optical package. Interconnects between dielectric and silicon substrate are created via TSVs and metal-metal bonding technology. The magnified view on a single X-junction on the right shows the parts of the SiP necessary for the required ion transport and qubit operations in a large-scale TIQC processor. Parts of the trap chiplet are cut off to provide open view on the optical and electrical signal fan-out and ion addressing zone.
• Figure 3: ⓐ: Illustration of a qubit addressing building block, consisting of a slotted trap chiplet with a glass substrate stacked on a PIC chiplet with a silicon substrate. The slot in the trap chiplet houses an integrated lens stack. ⓑ: Exploded view of the addressing building block without the trap chiplet showing the integrated lens stack that serves as the laser focusing unit. A deflecting element realized on the PIC chiplet redirects the laser beams from waveguides towards the lens stack. ⓒ: Scanning electron microscopy cross section of aluminum filled TSVs electrically interfacing trap chiplet front and back side. ⓓ: Magnified top and bottom part of one TSV, showing no delamination of the aluminum from the substrate after several cool-down cycles to liquid nitrogen temperature.
• Figure 4: ⓐ: Demonstrator CAD design of the integrated qubit addressing building block. ⓑ, ⓒ: Half-cuts through the CAD design at the focusing unit position in YZ-plane and XZ-plane, respectively. ⓓ: Microscopy image of a fabricated focusing unit on a PIC chiplet. ⓔ(left): Illustration of a TIR mirror structure for a single waveguide and pointing vector of the light propagation. ⓔ(right): Finite-difference time-domain simulation of the light propagation through the TIR mirror structure for a single waveguide.
• Figure 5: ⓐ: Beam profile of one of the optical channels of the integrated addressing unit showing the light propagation in x- and y-direction around the focal spot. ⓑ: 2D plot of the focal spot at the ion location and 1D slices in x- and y-direction with Gaussian fit functions. The mode field diameter (MFD) in x- and y-direction at the focal spot is determined with MFD$_x$ = (1.73$\pm$0.01) µ m and MFD$_y$ = (3.42$\pm$0.02) µ m, respectively.