Accurate Modeling of Gate Leakage Currents in SiC Power MOSFETs
Ang Feng, Alexander Karl, Dominic Waldhör, Marina Avramenko, Peter Moens, Tibor Grasser
TL;DR
This work tackles gate leakage in SiC MOS devices by developing a self-consistent physics-based framework that couples electrostatics, quantum tunneling, 1D Boltzmann transport, impact ionization, and nonradiative multiphonon hole trapping within the Comphy platform. The approach yields quantitative agreement with gate-leakage $J_g$-$V_g$ measurements across 80–573 K without empirical fitting, revealing that electron-initiated impact ionization in the a-SiO$_2$ oxide generates electron–hole pairs and that captured holes amplify leakage, shifting the flat-band condition. A key finding is that the conduction-band offset $\Phi_c(T)$ acts as the tunneling barrier rather than the combined barrier $\Phi_{\text{eff}}(T)$, highlighting the role of Fermi-level offsets in thick oxides. The framework provides a predictive tool for oxide reliability and lifetime projections in wide-bandgap devices and is applicable to advanced Si CMOS processes that share the same gate dielectric stack.
Abstract
Silicon carbide (SiC) metal-oxide-semiconductor field-effect-transistors (MOSFETs) enable high-voltage and high-temperature power conversion. Compared to Si devices, they suffer from pronounced gate leakage due to the reduced electron tunneling barrier at the interface between SiC and amorphous silicon dioxide (a-SiO$_2$). We develop a self-consistent, physics-based simulation framework that couples electrostatics, quantum tunneling, carrier transport, impact ionization, and charge trapping for both electrons and holes. The model quantitatively reproduces measured gate-current-voltage characteristics of SiC MOS capacitors over a wide temperature (80-573 K) range and a wide bias range without empirical fitting. Simulations reveal that conduction electrons in a-SiO$_2$ can trigger impact ionization, which generates electron-hole pairs, and leads to capture of holes in the oxide bulk, thereby enhancing gate leakage current. The framework captures these coupled processes across multiple orders of magnitude in time and field, providing predictive capability for oxide reliability. Although demonstrated for SiC devices, the methodology also applies to Si technologies that uses the same gate dielectric.
