Drafting and Multi-Input Switching in Digital Dynamic Timing Simulation for Multi-Input Gates

TL;DR

The paper addresses the need for accurate dynamic timing analysis that accounts for multi-input switching and drafting effects in digital circuits.It extends the Involution Tool with a thresholded hybrid model to derive closed-form analytic delay formulas \delta_\uparrow(T,\Delta) and \delta_\downarrow(T,\Delta) for interconnected 2-input NOR gates and provides a straightforward parametrization requiring only three MIS delay values.A complete simulation algorithm processes input transitions to produce output transitions using these formulas, and a full NAND model is obtained via De Morgan duality, enabling modeling of common gate families beyond NOR.Experimental results on cross-coupled NOR chains and a c_17_slack-like circuit demonstrate marked accuracy gains over inertial and IDM approaches while preserving fast, discrete-event simulation performance.

Abstract

We present a prototype multi-input gate extension of the publicly available Involution Tool for accurate digital timing simulation and power analysis of integrated circuits introduced by Oehlinger et al. (Integration, 2021). Relying on discrete event simulation, the Involution Tool allows fast timing simulation of circuits made up of an arbitrary composition of supported gates, provides automatic random input stimulus generation, and supports parameter sweeping. It also enables a detailed comparison of the delay predictions obtained by different models, including pure and inertial delays as well as digitized SPICE-generated reference traces. Our extension added support for 2-input gates like NOR and NAND, by implementing novel analytic delay formulas obtained via a refined analysis of a recently proposed thresholded first-order hybrid model of such gates. The resulting formulas faithfully cover not only multi-input switching effects (also known as Charlie effects), but also the decay of short pulses (aka Drafting effects). Besides the fact that our analytic models not only allow the derivation of closed-form delay formulas for arbitrary compositions of such gates, they are also key for a strikingly simple procedure for model parametrization, i.e., for gate characterization, which only needs three characteristic delay values. Using the extended Involution Tool, we compare the delay and power predictions for some benchmarking circuits stimulated by randomly generated input traces. Overall, our results reveal considerably improved prediction accuracy compared to the original Involution Tool, without a noticeable performance penalty.

Figures (13)

• Figure 1: Illustration of the thresholded hybrid system of an IDM channel, with a single input $i$ and output $o$. It comprises an (optional) pure delay shifter, producing $i_d$, and two ODEs governing some state signal $x(t)$ that is digitized by a threshold voltage comparator to produce $o$. The active ODE is selected by the current state of $i_d$, with mode switches that guarantee continuity of $x(t)$.
• Figure 2: Measured waveform for a $90$nm CMOS inverter chain, with the predictions according to the IDM (red long up/down-arrows) and the DDM (blue short up/down arrows). Taken from FNNS19:TCAD.
• Figure 3: Measured $\delta_\downarrow$ (blue) and $\delta_\uparrow$ (red) for the $90$nm CMOS inverter chain that produced \ref{['fig:wave90_inv']}. Taken from FNNS19:TCAD
• Figure 4: MIS effects in the measured delay of a $15$nm technology CMOS NOR gate.
• Figure 5: Transistor schematic and the resistor model of a CMOS NOR gate along with its augmented RC interconnect component.

Theorems & Definitions (5)

• Proposition 4.1: Output voltage trajectories for the interconnect-augmented NOR gate ferdowsi2024hybrid
• Proposition 4.2: MIS delay functions for the interconnect-augmented NOR gate ferdowsi2024hybrid
• Proposition 4.3: Model parametrization for interconnect-augmented NOR gates ferdowsi2024hybrid
• Theorem 5.1: Trajectory resp. delay formulas for interconnected NOR gates, used in \ref{['Alg:NOR']}
• proof