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Logic Encryption: This Time for Real

Rupesh Raj Karn, Lakshmi Likhitha Mankali, Zeng Wang, Saideep Sreekumar, Prithwish Basu Roy, Ozgur Sinanoglu, Lilas Alrahis, Johann Knechtel

TL;DR

This work challenges conventional logic locking by introducing logic encryption (LE) that cryptographically encryption of the entire gate-level netlist. It provides an end-to-end LE pipeline—gate encoding, AES-based encryption, a correction circuit, randomization, and system-level MUX obfuscation—ensuring correct functionality only with the proper key. Extensive evaluations against oracle-less attacks (OMLA, MuxLink, SCOPE, GNN-RE) on standard benchmarks show LE delivers strong resilience with competitive PPA overheads, outperforming prior schemes. The paper also releases open-source tooling and discusses implications for real-world IP protection and future extensions to interconnect encryption and oracle-guided threat models.

Abstract

Modern circuits face various threats like reverse engineering, theft of intellectual property (IP), side-channel attacks, etc. Here, we present a novel approach for IP protection based on logic encryption (LE). Unlike established schemes for logic locking, our work obfuscates the circuit's structure and functionality by encoding and encrypting the logic itself. We devise an end-to-end method for practical LE implementation based on standard cryptographic algorithms, key-bit randomization, simple circuit design techniques, and system-level synthesis operations, all in a correct-by-construction manner. Our extensive analysis demonstrates the remarkable efficacy of our scheme, outperforming prior art against a range of oracle-less attacks covering crucial threat vectors, all with lower design overheads. We provide a full open-source release.

Logic Encryption: This Time for Real

TL;DR

This work challenges conventional logic locking by introducing logic encryption (LE) that cryptographically encryption of the entire gate-level netlist. It provides an end-to-end LE pipeline—gate encoding, AES-based encryption, a correction circuit, randomization, and system-level MUX obfuscation—ensuring correct functionality only with the proper key. Extensive evaluations against oracle-less attacks (OMLA, MuxLink, SCOPE, GNN-RE) on standard benchmarks show LE delivers strong resilience with competitive PPA overheads, outperforming prior schemes. The paper also releases open-source tooling and discusses implications for real-world IP protection and future extensions to interconnect encryption and oracle-guided threat models.

Abstract

Modern circuits face various threats like reverse engineering, theft of intellectual property (IP), side-channel attacks, etc. Here, we present a novel approach for IP protection based on logic encryption (LE). Unlike established schemes for logic locking, our work obfuscates the circuit's structure and functionality by encoding and encrypting the logic itself. We devise an end-to-end method for practical LE implementation based on standard cryptographic algorithms, key-bit randomization, simple circuit design techniques, and system-level synthesis operations, all in a correct-by-construction manner. Our extensive analysis demonstrates the remarkable efficacy of our scheme, outperforming prior art against a range of oracle-less attacks covering crucial threat vectors, all with lower design overheads. We provide a full open-source release.

Paper Structure

This paper contains 21 sections, 19 equations, 9 figures, 2 tables.

Figures (9)

  • Figure 1: Our approach for revisiting LE is fundamentally different from prior art of LL. Instead of integrating KG structures into the netlist as an afterthought, our work encrypts the netlist itself, utilizing cryptographic algorithms and simple circuit design techniques, all to fully obfuscate the design IP with competitive overheads.
  • Figure 2: End-to-end method for LE, separated into key stages.
  • Figure 3: Obfuscation of system-level interconnects between the encrypted circuit and the correction circuit.
  • Figure 4: Test accuracy [%] for OMLA.
  • Figure 5: Test accuracy [%] for MuxLink.
  • ...and 4 more figures