On-Chip Levitated Neon Particle Arrays for Robust and Scalable Electron Qubits

TL;DR

The paper addresses the challenge of reproducible, scalable electron qubits bound to neon surfaces by introducing an on-chip magnetic-levitation architecture that suspends solid-neon microparticles above the processor to host electrons, thereby eliminating substrate roughness as a decoherence source. The approach enables strong qubit–resonator coupling, GHz-frequency tunability of the qubit transition via the resonator bias and geometry, and large positive anharmonicity, while maintaining compatibility with superconducting resonators and potential for resonator-mediated two-qubit gates. Key results show achievable qubit transition frequencies in the few-GHz range, anharmonicities α/h up to about 0.8 GHz, and robust g couplings (>5 MHz) with prospects for tens of MHz using high-impedance resonators; dispersive two-qubit coupling strengths J ~ 2–6 MHz are predicted for practical detunings. The work suggests a robust, reproducible, and scalable eNe platform, with potential extensions to spin qubits and hybrid quantum networks leveraging neon’s nuclear-spin-free isotopes and compatible quantum-fluid carriers.

Abstract

Electron-on-neon (eNe) qubits have recently emerged as a compelling platform for quantum computing, which combines the vacuum isolation advantages of trapped-ion qubits with the scalability of superconducting circuits. In this system, electrons are trapped in vacuum above a solid neon film deposited on superconducting microwave resonators, where they exhibit strong coupling to the resonators, coherence times of ~0.1 ms, and single-qubit gate fidelities exceeding 99.97%. A central challenge, however, is the spontaneous binding of electrons to neon surface bumps. These bumps, originating from substrate roughness, vary in size: electrons on bumps of suitable sizes within the resonator can couple to microwave photons and function as qubits, whereas those on unfavorable bumps remain inactive yet contribute to background charge noise. Moreover, both the bump landscape and the sites where electrons bind differ from run to run, leading to variable qubit characteristics that hinder scalability. To address this challenging issue, we present an on-chip magnetic-levitation architecture in which arrays of solid-neon microparticles are suspended above the processor chip to act as electron carriers. This design eliminates substrate effects while retaining strong qubit-resonator coupling and supporting inter-qubit connectivity. Our analysis further shows that the qubit transition frequency can be tuned across the gigahertz range and its anharmonicity can reach ~0.8 GHz by tuning the resonator bias voltage. Together, these features suggest a promising pathway toward robust, reproducible, and scalable eNe-based quantum computing.

Figures (13)

• Figure 1: (a) Schematic showing the Pauli barrier and surface-bound state of an electron on He II or solid neon. (b) Schematic of a typical He II–filled microchannel device for trapping and controlling a surface electron Koolstra2019.
• Figure 2: (a) Schematic wavefunction profiles of an electron self-bound to a SNe surface bump in the ground state $\ket{0}$ and first excited state $\ket{1}$Kanai2024. (b) Cross-sectional schematic of the device in Fig. \ref{['Fig1']}(b), showing electrons bound to surface bumps on the SNe film deposited on the device. (c) Conceptual diagram of the proposed on-chip architecture using arrays of magnetically levitated SNe microparticles as electron qubit carriers.
• Figure 3: (a) Schematic showing the HTS loop parameters used in the analysis. (b) Calculated potential energy density $E(\mathbf{r})$ for solid neon in the magnetic field generated by a current loop with the specified parameters. Contours are plotted with an energy density interval of $3.94\times10^{-3}$ J/m$^3$.
• Figure 4: (a) The height of the levitation point $z_L$ as a function of $I$ for the loop analyzed in Fig. \ref{['Fig3']}(b). (b) Calculated trap volume $V_{\text{trap}}$ as a function of $I$ and $B_0$ for two loops of different sizes. (c) Schematic of the device near a levitation site.
• Figure 5: Schematic showing the mist merging method for loading SNe particles on the chip in the experimental chamber.