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Extended Abstract: Synthesizable Low-overhead Circuit-level Countermeasures and Pro-Active Detection Techniques for Power and EM SCA

Archisman Ghosh

TL;DR

The work tackles power and EM side-channel vulnerabilities in embedded cryptography by proposing low-overhead, synthesizable defenses. It combines Digital Signature Attenuation with on-chip self-awareness and ML-based detection to proactively counter EMSCA and FIA, plus an intelligent voltage-drop detector to thwart adaptive attacks. A silicon-verified Saber PQC accelerator employing Striding Toom-Cook with Lazy Interpolation demonstrates substantial reductions in power, memory, and energy, illustrating practical viability for NIST PQC candidates in 65nm silicon. Overall, the paper advances energy-efficient, hardware-based defenses for IoT cryptography and lattice-based post-quantum implementations.

Abstract

The gamut of todays internet-connected embedded devices has led to increased concerns regarding the security and confidentiality of data. Most internet-connected embedded devices employ mathematically secure cryptographic algorithms to address security vulnerabilities. Despite such mathematical guarantees, as these algorithms are often implemented in silicon, they leak critical information in terms of power consumption, electromagnetic (EM) radiation, timing, cache hits and misses, photonic emission and so on, leading to side-channel analysis (SCA) attacks. This thesis focuses on low overhead generic circuit-level yet synthesizable countermeasures against power and EM SCA. Existing countermeasures (including proposed) still have relatively high overhead which bars them from being used in energy-constraint IoT devices. We propose a zero-overhead integrated inductive sensor which is able to detect i)EM SCA ii) Clock glitch-based Fault Injection Attack (FIA), and iii) Voltage-glitch based Fault Injection Attack by using a simple ML algorithm. Advent of quantum computer research will open new possibilities for theoretical attacks against existing cryptographic protocols. National Institute of Standard & Technology (NIST) has standardized post-quantum cryptographic algorithms to secure crypto-systems against quantum adversary. I contribute to the standardization procedure by introducing the first silicon-verified Saber (a NIST finalist modulo Learning with Rounding scheme) which consumes lowest energy and area till date amongst all the candidates.

Extended Abstract: Synthesizable Low-overhead Circuit-level Countermeasures and Pro-Active Detection Techniques for Power and EM SCA

TL;DR

The work tackles power and EM side-channel vulnerabilities in embedded cryptography by proposing low-overhead, synthesizable defenses. It combines Digital Signature Attenuation with on-chip self-awareness and ML-based detection to proactively counter EMSCA and FIA, plus an intelligent voltage-drop detector to thwart adaptive attacks. A silicon-verified Saber PQC accelerator employing Striding Toom-Cook with Lazy Interpolation demonstrates substantial reductions in power, memory, and energy, illustrating practical viability for NIST PQC candidates in 65nm silicon. Overall, the paper advances energy-efficient, hardware-based defenses for IoT cryptography and lattice-based post-quantum implementations.

Abstract

The gamut of todays internet-connected embedded devices has led to increased concerns regarding the security and confidentiality of data. Most internet-connected embedded devices employ mathematically secure cryptographic algorithms to address security vulnerabilities. Despite such mathematical guarantees, as these algorithms are often implemented in silicon, they leak critical information in terms of power consumption, electromagnetic (EM) radiation, timing, cache hits and misses, photonic emission and so on, leading to side-channel analysis (SCA) attacks. This thesis focuses on low overhead generic circuit-level yet synthesizable countermeasures against power and EM SCA. Existing countermeasures (including proposed) still have relatively high overhead which bars them from being used in energy-constraint IoT devices. We propose a zero-overhead integrated inductive sensor which is able to detect i)EM SCA ii) Clock glitch-based Fault Injection Attack (FIA), and iii) Voltage-glitch based Fault Injection Attack by using a simple ML algorithm. Advent of quantum computer research will open new possibilities for theoretical attacks against existing cryptographic protocols. National Institute of Standard & Technology (NIST) has standardized post-quantum cryptographic algorithms to secure crypto-systems against quantum adversary. I contribute to the standardization procedure by introducing the first silicon-verified Saber (a NIST finalist modulo Learning with Rounding scheme) which consumes lowest energy and area till date amongst all the candidates.

Paper Structure

This paper contains 6 sections, 1 figure.

Table of Contents

  1. Introduction
  2. Power & EM SCA security by Digital Signature Attenuation
  3. Self-Awareness: EMSCA & FIA Detection by single on-chip loop & ML algorithm
  4. Sustainable Signature Attenuation Technique with intelligent voltage drop attack detector
  5. 1st Silicon Verified ASIC of Saber with Striding Toom-Cook multiplication with Lazy Interpolation
  6. Acknowledgment & Notes

Figures (1)

  • Figure 1: a) 65nm CMOS IC for digital signature attenuation technique and single on-chip sensor for EM SCA & FIA detection. b) 65nm CMOS IC for sustainable digital signature attenuation circuit with intelligent attack detector. c) 1st Silicon verified Saber IC and architecture.