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A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions

Amogh K M, Sunita M S

TL;DR

The paper tackles the energy cost of data movement in Von-Neumann systems by proposing an SRAM-based in-memory computing architecture built on an 8×8 array of 8T cells. It decouples read and write paths to improve reliability over 6T designs and uses charge-sharing on dedicated read bit-lines to perform multi-bit MAC operations, with a MAC decoder converting the analog MAC output into an 8-bit count. This MAC count is then used to infer fundamental logic functions (AND/NAND, NOR/OR, XOR/XNOR) and 1-bit addition without extra logic circuits. Cadence Virtuoso simulations in 90 nm at 1.8 V show 8-bit MAC and derived logic operating at 142.85 MHz with 0.7 ns latency and throughput of 15.8 Mops/s, achieving energy efficiency around 56.56 fJ/bit and highlighting the approach's potential for energy-efficient edge AI. The work demonstrates a practical route to integrating storage and computation in mature SRAM technology, enabling densely parallel MAC and logic within memory arrays.

Abstract

This paper presents an in-memory computing (IMC) architecture developed on an 8x8 array of 8T SRAM cells. This architecture enables both multi-bit parallel Multiply-Accumulate (MAC) operations and standard memory processing through charge-sharing on dedicated read bit-lines. By leveraging the maturity of SRAM technology, this work introduces an 8T SRAM-based IMC architecture that decouples read and write paths, thereby overcoming the reliability limitations of prior 6T SRAM designs. A novel analog-to-digital decoding scheme converts the MAC voltage output into digital counts, which are subsequently interpreted to realize fundamental logic functions including AND/NAND, NOR/OR, XOR/XNOR, and 1-bit addition within the same array. Simulated in a 90 nm CMOS process at 1.8 V supply voltage, the proposed design achieves 8-bit MAC and logical operations at a frequency of 142.85 MHz, with a latency of 0.7 ns and energy consumption of 56.56 fJ/bit per MAC operation and throughput of 15.8 M operations/s.

A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions

TL;DR

The paper tackles the energy cost of data movement in Von-Neumann systems by proposing an SRAM-based in-memory computing architecture built on an 8×8 array of 8T cells. It decouples read and write paths to improve reliability over 6T designs and uses charge-sharing on dedicated read bit-lines to perform multi-bit MAC operations, with a MAC decoder converting the analog MAC output into an 8-bit count. This MAC count is then used to infer fundamental logic functions (AND/NAND, NOR/OR, XOR/XNOR) and 1-bit addition without extra logic circuits. Cadence Virtuoso simulations in 90 nm at 1.8 V show 8-bit MAC and derived logic operating at 142.85 MHz with 0.7 ns latency and throughput of 15.8 Mops/s, achieving energy efficiency around 56.56 fJ/bit and highlighting the approach's potential for energy-efficient edge AI. The work demonstrates a practical route to integrating storage and computation in mature SRAM technology, enabling densely parallel MAC and logic within memory arrays.

Abstract

This paper presents an in-memory computing (IMC) architecture developed on an 8x8 array of 8T SRAM cells. This architecture enables both multi-bit parallel Multiply-Accumulate (MAC) operations and standard memory processing through charge-sharing on dedicated read bit-lines. By leveraging the maturity of SRAM technology, this work introduces an 8T SRAM-based IMC architecture that decouples read and write paths, thereby overcoming the reliability limitations of prior 6T SRAM designs. A novel analog-to-digital decoding scheme converts the MAC voltage output into digital counts, which are subsequently interpreted to realize fundamental logic functions including AND/NAND, NOR/OR, XOR/XNOR, and 1-bit addition within the same array. Simulated in a 90 nm CMOS process at 1.8 V supply voltage, the proposed design achieves 8-bit MAC and logical operations at a frequency of 142.85 MHz, with a latency of 0.7 ns and energy consumption of 56.56 fJ/bit per MAC operation and throughput of 15.8 M operations/s.

Paper Structure

This paper contains 19 sections, 6 figures, 5 tables.

Table of Contents

  1. Introduction
  2. 8T SRAM CELL AND ARRAY ARCHITECTURE
  3. Key Idea
  4. 8T SRAM Cell Architecture
  5. 8×8 IMC Array
  6. MAC Decoder Circuit
  7. MULTIPLY-ACCUMULATE AND LOGIC OPERATIONS
  8. Multiply and Accumulate Operation
  9. Interpreting AND/NAND from MAC Count
  10. Interpreting NOR/OR from MAC Count
  11. Interpreting XOR/XNOR from MAC Count
  12. Implementation of 1-Bit Addition Operation
  13. Scalability
  14. Results
  15. MAC Simulation
  16. ...and 4 more sections

Figures (6)

  • Figure 1: 8T SRAM cell architecture.
  • Figure 2: 8×8 IMC array.
  • Figure 3: MAC decoder circuit
  • Figure 4: Voltage comparator circuit.
  • Figure 5: Output waveform for the 8-bit MAC operation
  • ...and 1 more figures