Wafer-Scale Single-Crystalline Monolayer Graphene

Abstract

Producing large-area single-crystalline graphene is key to realizing its full potential in advanced applications, including twistronics. Yet, controlling graphene growth kinetics to avoid grain boundaries or multilayer growth remains challenging. Here, we demonstrate single-crystalline graphene free from multilayer domains via one-step delamination of epitaxial graphene from silicon carbide (SiC). This is enabled by a specific surface reconstruction of 4H-SiC(0001) achieved in our growth conditions. High crystalline quality is confirmed by the observation of the half-integer quantum Hall effect -- the hallmark of monolayer graphene -- in near cm-sized crystals. The scalability of our process, explored with 4''-wafers, represents an advance toward large-scale integration of high-performance graphene applications.

Figures (19)

• Figure 1: Production of single-crystalline monolayer graphene. (A) Illustration of delamination of epigraphene from a Type A SiC surface, where excess graphene patches are left behind on the substrate, i.e. on the buffer layer. (B) AFM topography map of the Type A SiC-substrate after graphene delamination, where all the excess graphene patches remain after delamination; these are overlaid in false-color (blue). (C) Terrace width histogram obtained from AFM data, normalized to probability, for Type A and B SiC surface reconstructions. (D) Same as (C) for step height. (E) Optical micrograph of epigraphene delaminated from a Type A SiC substrate and transferred to SiO$_2$/Si. Note the absence of graphene patches. (F) Same as (E) with graphene delaminated from a Type B surface, where bilayer patches co-delaminated with the top graphene layer.
• Figure 2: Surface characterization of graphene delaminated from SiC. (A) Raman spectra (532 nm laser) for as-grown epigraphene on SiC (black line) along with the 4H-SiC substrate underneath the graphene (green line), and graphene transferred from SiC to SiO$_2$/Si using different metals (gold, silver, and nickel). (B) SAED pattern of graphene transferred from SiC onto a holey carbon TEM grid. The hexagonal spot array represents graphene with lattice parameter $a=2.54$$\pm 0.02$ Å. The diffuse halo is characteristic of amorphous carbon of the TEM grid. (C) ARPES band structure for as-grown graphene on SiC represented as an energy–momentum cut through the $\bar{K}$-point in the Brillouin zone as indicated in the inset. The dotted line is a linear fit to the band dispersion close to the Fermi level used to extract the Fermi velocity. (D) Same as (C) for graphene transferred to SiO$_2$/Si. As a consequence of the polarization of the light, only one branch of the band structure is visible Gierz2011IlluminatingGraphene.
• Figure 3: Electrical transport in graphene transferred from SiC onto SiO$_2$/Si. (A) Hall bar with gold-transferred graphene ($W = 5\, \mu$m, $L = 15\,\mu$m) and passivated with PMMA. (B) Sheet resistivity vs. gate voltage at $T=300$ K (blue dots) and $T=2$ K (purple squares); solid lines are FET mobility fits. (C) Hall mobilities vs. carrier densities at $T=300$ K (blue dots) and $T=2$ K (magenta triangles). Solid lines are fits to Eq. \ref{['mobility_vs_n_linearized']}. (D) Half-integer QHE at $B=14$ T and $T=2$ K showing $\nu=2,6,10$. (E) Temperature dependence of SdH-oscillations for electrons ($V_g=60$ V; $n = 3.8\times10^{12}$ cm$^{-2}$). (F) Landau index plot from SdH $\rho_{xx}$-minima at 2 K for holes ($V_g = -44$ V) and electrons ($V_g = 60$ V). (G) Large-area device with silver-transferred graphene on SiO$_2$/Si. (H) Half-integer QHE at $B=14$ T, $T=2$ K in the large-area device. (I) Zero-resistance state ($\rho_{xx}=0$) in I-V-curves measured at the $\nu = \pm 2$-plateaus ($B=14$ T) for electrons ($V_g = 35$ V) and holes ($V_g = 15$ V) for $I_{xx}>0$. The dashed line indicates the noise floor ($V_{rms} = 83$ nV).
• Figure 4: Delamination and transfer of wafer-scale epigraphene. (A) As-grown epigraphene on a recycled 4" SiC wafer. (B) A representative 15$\times$15 $\mu$m$^2$ AFM phase map of epigraphene grown on a 4"-SiC wafer, showing the presence of bilayer domains (dark) that covers 40% of the total area. (C) 4"-sized graphene transferred from SiC to a 4"-SiO$_2$/Si wafer. (D) Optical micrograph of graphene transferred from the 4"-SiC wafer to SiO$_2$/Si (C), showing the presence of bilayer domains (dark stripes) on monolayer graphene that cover 1% of the area. (E) Mapping of percentage bilayer graphene over the SiO$_2$/Si wafer (see panel C) with the median value $4.3\%$. Each square corresponds to an area of $290 \times 190$$\mu$m$^2$; the white regions correspond to areas with no graphene. (F) Schematic illustration of epigraphene on SiC within our growth model. The black circles represent anchor points of graphene patches or the buffer layer to the substrate.
• Figure S1: Atomic Force microscopy characterization of graphene on SiC before and after delamination of the top graphene layer, demonstrating that all graphene patches remain on the substrate after graphene delamination. (A) Topography map, scan size $10\times10$$\mu$m$^2$, of graphene on SiC. (B) Adhesion force mapping on graphene on SiC, measured separately along with the topography measurement in A. Dark color represents bilayer patches on graphene. (C) Topography scan of the same area as in A and B but after delamination of the top graphene layer. (D) Adhesion map of graphene on SiC, measured along with topography in C. The lighter color corresponds to the remaining (100%) monolayer graphene patches.