Classification of coherent peaks in two-terminal quantum devices into normal and anomalous Kondo peaks

TL;DR

The paper addresses how coherent peaks in two-terminal quantum devices can be categorized by their scaling behavior into normal and anomalous Kondo peaks. It extends scaling analyses to finite-bias, derives a Liouville-space Green’s-function framework to compute differential conductance, and demonstrates that ZBPs in the QDSET odd sector originate from two coherent side peaks—consistent with QPC observations—while ZBPs with spin exchange follow a different scaling. The key contributions are the identification of two scaling functions $G_{ m I}(T)$ and $G_{ m II}(T)$, the introduction of distinct Kondo temperatures $T_{ m NK}$ and $T_{ m AK}$, and the reproduction of experimental line shapes, which collectively clarify the mechanisms behind ZBPs and coherent peaks in nanoscale devices. This work provides a practical framework for interpreting Kondo-related features in quantum dots and quantum point contacts and highlights the role of entangled-state tunneling in shaping finite-bias conductance.

Abstract

Coherent peaks arising in the differential conductance of quantum dot (QD) and quantum point contact (QPC) devices are classified into two categories, normal and anomalous Kondo peaks, according to the underlying spin dynamics and the form of the scaling function to which the scaled temperature-dependent linear conductance collapses. The zero-bias peaks (ZBPs) observed in QPCs and in the triplet state of the even sector of quantum dot single-electron transistors (QDSETs) are identified as normal Kondo peaks, formed by spin dynamics involving spin exchange, a symbolic characteristic of the Kondo effect. For these ZBPs, the scaling temperature coincides with half the full width at half maximum (FWHM). In contrast, the ZBP observed in the odd sector of QDSETs and all finite-bias coherent peaks, including the coherent side peaks of QPCs and the split ZBP in the singlet state of the QDSET even sector, are identified as anomalous Kondo peaks, because they arise from spin dynamics without spin exchange, and their scaling temperature does not coincide with half the FWHM. To support these findings, we reproduce gate-voltage-dependent differential conductance line shapes measured in the odd sector of a QDSET, demonstrating that its ZBP originates from a combination of two coherent side peaks explicitly observed in QPCs.

Figures (6)

• Figure 1: Schematic illustration of a two-terminal nanodevice in which transport occurs via entangled-state tunneling formed by a linear combination of two Kondo singlets. $U$ denotes the Coulomb repulsion at the position of the localized spin and $V_{\rm G}$ the side-gate voltage. Solid dots represent the coherent spins at the Fermi levels of the reservoirs.
• Figure 2: (a) Temperature-dependent finite-bias linear conductance scaled by $T_{\rm AK}$ for different gate voltages, plotted as a function of $T/T_{\rm AK}$. The scaling behavior of the zero-bias anomaly from reference Cronenwett, scaled by $T_{\rm NK}$, is shown for comparison. The black and magenta curves represent $G_{\rm I}(T)$ and $G_{\rm II}(T)$, respectively. Data sources and $T_{\rm AK}$ values are provided. (b) Same as (a), but for data extracted from line shapes at the singlet (red circles and green triangles) and triplet (dark squares) states in the QDSET even sector Roch.
• Figure 3: The curve of equation (\ref{['Cond-scale']}) (green line) and temperature-dependent linear conductance data (open squares) from Fig. 4b of reference Roch. The red square represents the linear conductance at 37 mK from Fig. 4a of reference Roch.
• Figure 4: Spin dynamics of unidirectional entangled-state tunneling with ($\gamma^{L,R}$) and without ($\gamma^{LR}_{S,A}$) spin exchange.
• Figure 5: (a) Schematic of the CNT QDSET. A highly doped Si wafer and a SiO$_2$ layer are used as a back gate and an insulating barrier, respectively. The CNT channel length is designed to be 300 nm with a diameter of approximately 1.5 nm. (b) Experimental differential conductance curves (solid lines) and theoretically reproduced curves (dashed lines) fitted on the left side for several gate voltages. Theoretical results are shifted to match the experimental peak positions. (c) Gray-scale plot of differential conductance as a function of source–drain bias $V$ and gate voltage $V_{\rm G}$.