Variable Point: A Number Format for Area- and Energy-Efficient Multiplication of High-Dynamic-Range Numbers

TL;DR

The paper introduces Variable-Point (VP), a number format that augments dynamic range without the overhead of floating-point, by using an M-bit signed significand and an E-bit exponent index into a custom exponent list. VP arithmetic reduces multiplication to significand operations with offline-exponent handling, enabling efficient MVM for high-dynamic-range signals and allowing per-signal parameter optimization. Through a beamspace MU-MIMO case study and post-layout 22 nm VLSI results, VP demonstrates up to ~20% area and ~10–14% power savings versus optimized FXP, and ~3.4× area reduction versus a custom floating-point design. The work also details FXP/VP conversion hardware, parameter selection strategies, and CSPADE-based optimizations, underscoring VP's practical viability for specialized accelerators and communications hardware.

Abstract

Fixed-point number representation is commonly employed in digital VLSI designs that have stringent hardware efficiency constraints. However, fixed-point numbers cover a relatively small dynamic range for a given bitwidth. In contrast, floating-point numbers offer a larger dynamic range at the cost of increased hardware complexity. In this paper, we propose a novel number format called variable-point (VP). VP numbers cover a larger dynamic range than fixed-point numbers with similar bitwidth, without notably increasing hardware complexity -- this allows for a more efficient representation of signals with high dynamic range. To demonstrate the efficacy of the proposed VP number format, we consider a matrix-vector multiplication engine for spatial equalization in multi-antenna wireless communication systems involving high-dynamic-range signals. Through post-layout VLSI implementation results, we demonstrate that the proposed VP-based design achieves 20% and 10% area and power savings, respectively, compared to a fully optimized fixed-point design, without incurring any noticeable performance degradation.

Figures (11)

• Figure 1: An example of a VP number $x$ with $M=6$ significand bits and $E=2$ exponent bits and the exponent list $\mathbf{f}\xspace=[3,2,0,-1]$.
• Figure 2: Two examples illustrating the conversion from FXP$(8,1)$ to VP$(6,[1,-1])$. The shaded bits show the significand of the converted VP number and the exponent index is shown separately.
• Figure 3: Architecture of FXP2VP converter parameterized by $\{(W, F), (M, \mathbf{f}\xspace)\}$. The converter takes the FXP input $x$ and produces the significand $m$ and the exponent index $i$ of the corresponding VP number.
• Figure 4: An example illustration of conversion from VP$(9,[3,1,2,0])$ to FXP$(12,3)$. For each of the four exponent options, we put the significand in the appropriate bit range of the output FXP number, and sign extend (SE) the remaining MSBs and zero-pad (ZP) the remaining LSBs.
• Figure 5: Architecture of VP2FXP converter parameterized by $\{(W, F), (M, \mathbf{f}\xspace)\}$. The converter takes the significand $m$ and the exponent index $i$ and produces the corresponding FXP number $\texttt{x}$.