From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors

TL;DR

This tutorial surveys the architectural evolution of digital neuromorphic processors through the SENECA platform, starting from an array of tiny RISC-V cores connected by a simple NoC and progressively adding accelerators like Neural Processing Elements and a loop controller. It emphasizes event-driven processing, spike-based software optimizations, and CNN-friendly mappings (e.g., depth-first inference and hard attention) to achieve energy-efficient, scalable edge AI. Key contributions include practical design guidelines, quantified benchmarks comparing successive SENECA versions, and a coherent framework for balancing flexibility with performance. The work offers a roadmap for researchers and practitioners to design their own digital neuromorphic processors with incremental domain-specific acceleration while maintaining programmability and adaptability.

Abstract

Digital neuromorphic processors are emerging as a promising computing substrate for low-power, always-on EdgeAI applications. In this tutorial paper, we outline the main architectural design principles behind fully digital neuromorphic processors and illustrate them using the SENECA platform as a running example. Starting from a flexible array of tiny RISC-V processing cores connected by a simple Network-on-Chip (NoC), we show how to progressively evolve the architecture: from a baseline event-driven implementation of fully connected networks, to versions with dedicated Neural Processing Elements (NPEs) and a loop controller that offloads fine-grained control from the general-purpose cores. Along the way, we discuss software and mapping techniques such as spike grouping, event-driven depth-first convolution for convolutional networks, and hard-attention style processing for high-resolution event-based vision. The focus is on architectural trade-offs, performance and energy bottlenecks, and on leveraging flexibility to incrementally add domain-specific acceleration. This paper assumes familiarity with basic neuromorphic concepts (spikes, event-driven computation, sparse activation) and deep neural network workloads. It does not present new experimental results; instead, it synthesizes and contextualizes findings previously reported in our SENECA publications to provide a coherent, step-by-step architectural perspective for students and practitioners who wish to design their own digital neuromorphic processors.

Figures (9)

• Figure 1: Examples of several digital neuromorphic chips. All follow the same template of connecting many tiny processing elements to build a scalable distributed processing platform.
• Figure 2: Internal pipeline and architecture of IBEX, from iis-projects.ee.ethz.ch.
• Figure 3: On the left, you can see the initial version of our neuromorphic processing core, while on the right, you can see the complete platform created by linking the cores together. The core architecture is annotated with the area and energy figures in the GF-22nm FDSOI technology node.
• Figure 4: On the right, you can see a 4-layer neural network being mapped on 16 cores (color-coded). On the left, there is a routing table of the NoC in the core 5. The NoC processes the incoming packet based on the input port and the label it carries. It then routes them to one or several output ports, depending on the content of the routing table. The label is a part of the spike packet.
• Figure 5: Event-driven processing of a fully connected layer. Neurons with non-zero activations that generate a spike (event) are shown in red. These events move to the next layer and update the corresponding receiving neurons.