InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning

TL;DR

This work tackles the slow, heavy-cost ATPG problem in modern ICs by introducing InF-ATPG, which partitions circuits into fanout-free regions and uses a Quality-Value Graph Neural Network to provide ATPG-specific state representations to a reinforcement-learning agent. By modeling the task as an MDP and solving with a DQN that leverages QGNN embeddings, InF-ATPG achieves large reductions in backtracks and decision-sequence length while improving fault coverage. Experimental results on ISCAS-based benchmarks show up to 55% backtrack reduction versus gate-level ATPG and meaningful gains over ML baselines, with particularly strong performance on larger circuits. These findings indicate that coarse-grained, structure-aware RL with specialized circuit features can significantly speed up ATPG while maintaining or improving fault detection, suggesting practical potential for industrial deployment.

Abstract

Automatic test pattern generation (ATPG) is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns. As semiconductor technology progresses, traditional ATPG struggles with long execution times to achieve the expected fault coverage, which impacts the time-to-market of chips. Recent machine learning techniques, like reinforcement learning (RL) and graph neural networks (GNNs), show promise but face issues such as reward delay in RL models and inadequate circuit representation in GNN-based methods. In this paper, we propose InF-ATPG, an intelligent FFR-driven ATPG framework that overcomes these challenges by using advanced circuit representation to guide RL. By partitioning circuits into fanout-free regions (FFRs) and incorporating ATPG-specific features into a novel QGNN architecture, InF-ATPG enhances test pattern generation efficiency. Experimental results show InF-ATPG reduces backtracks by 55.06\% on average compared to traditional methods and 38.31\% compared to the machine learning approach, while also improving fault coverage.

Figures (6)

• Figure 1: Challenges in existing methods: (a) Long decision sequences lead to delayed rewards; (b) Inadequate circuit state representation for ATPG.
• Figure 2: Overview of the InF-ATPG framework. (a) Circuit partitioning into FFRs simplifies decision-making; (b) QGNN-based state representation improves the RL agent’s ability to generalize; (c) MDP and DQN modeling optimize test generation efficiency.
• Figure 3: Comparison of FFR-level and Gate-level backtrace. FFR-level backtrace shortens the decision sequence by directly targeting fanin gates, while Gate-level backtrace involves a longer sequence of intermediate gates.
• Figure 4: QGNN aggregation process across different logic states in an FFR. Nodes with 0, 1, and X logic values use different aggregators to propagate information, enhancing the model's ability to capture complex circuit dependencies.
• Figure 5: MDP and DQN process in InF-ATPG. The QGNN generates state embeddings, and the DQN evaluates action values, selects actions, and updates the model through reinforcement learning. Transitions are stored and sampled from a PER buffer to optimize learning efficiency.