A CNN-Based Technique to Assist Layout-to-Generator Conversion for Analog Circuits

TL;DR

The paper addresses the bottleneck in analog layout-to-generator conversion by introducing a CNN that predicts whether a sub-cell can be generated by existing scripts and, when possible, suggests the appropriate generator. It uses a multi-scale, 21-channel CNN trained on a mix of generated, random not-generatable, and realistic layouts to classify 4,885 sub-cell instances across 52 classes, achieving 99.3% precision on a high-speed RX dataset and strong performance on unseen TRX layouts. The approach dramatically reduces manual inspection time from 88 minutes to about 18 seconds and demonstrates robust generalization to unfamiliar sub-cells, with potential for automatic workflow integration and library growth. Overall, the method accelerates layout-to-generator development, enabling rapid iteration and reuse of silicon-proved designs.

Abstract

We propose a technique to assist in converting a reference layout of an analog circuit into the procedural layout generator by efficiently reusing available generators for sub-cell creation. The proposed convolutional neural network (CNN) model automatically detects sub-cells that can be generated by available generator scripts in the library, and suggests using them in the hierarchically correct places of the generator software. In experiments, the CNN model examined sub-cells of a high-speed wireline receiver that has a total of 4,885 sub-cell instances including different 145 sub-cell designs. The CNN model classified the sub-cell instances into 51 generatable and one not-generatable classes. One not-generatable class indicates that no available generator can generate the classified sub-cell. The CNN model achieved 99.3% precision in examining the 145 different sub-cell designs. The CNN model greatly reduced the examination time to 18 seconds from 88 minutes required in manual examination. Also, the proposed CNN model could correctly classify unfamiliar sub-cells that are very different from the training dataset.

Figures (16)

• Figure 1: The concept of layout-to-generator conversion, and example generation of sense-amplifiers using the procedural generator converted from the reference sense amplifier layout. For different input parameters, many different layout geometries such as the width/length/count of fingers and the number of vias can be modified.
• Figure 2: A reusing example of an inverter generator script during the development of the procedural generator of an inverter chain layout.
• Figure 3: An example of sub-cell layouts that can be generated with existing generator scripts. The example sense amplifier layout consists of 8 MOSFETs, 129 via stacks, and 79 boundary/path elements. The correct sub-cell generators must be assigned to 8 MOSFETs and 129 via stacks to develop the generator of the sense-amplifier.
• Figure 4: Basic Layout elements and parametric description formula. Reprinted from [4].
• Figure 5: An example hierarchical design flow of the layout-to-generator conversion framework with inverter example, reprinted from [4].