SetupKit: Efficient Multi-Corner Setup/Hold Time Characterization Using Bias-Enhanced Interpolation and Active Learning

TL;DR

This work targets the bottleneck of setup/hold time characterization across multiple PVT corners by introducing BEIRA, a bias-enhanced interpolation method, along with circuit-analysis-based interval estimation and active learning to guide costly SPICE simulations. BEIRA models interpolation error probabilistically and uses an optimal bias to avoid stagnation, while circuit analysis provides tight initial intervals and AL leverages cross-corner correlations to minimize simulations in multi-corner scenarios. Empirical results on a 22nm standard-cell library across 16 corners show a 2.4× overall CPU-time reduction, decreasing total characterization time from 720 to 290 days on a single core for 4 million points. The approach delivers a principled, learning-based pathway to faster, signoff-quality library characterization with scalable parallelization potential.

Abstract

Accurate setup/hold time characterization is crucial for modern chip timing closure, but its reliance on potentially millions of SPICE simulations across diverse process-voltagetemperature (PVT) corners creates a major bottleneck, often lasting weeks or months. Existing methods suffer from slow search convergence and inefficient exploration, especially in the multi-corner setting. We introduce SetupKit, a novel framework designed to break this bottleneck using statistical intelligence, circuit analysis and active learning (AL). SetupKit integrates three key innovations: BEIRA, a bias-enhanced interpolation search derived from statistical error modeling to accelerate convergence by overcoming stagnation issues, initial search interval estimation by circuit analysis and AL strategy using Gaussian Process. This AL component intelligently learns PVT-timing correlations, actively guiding the expensive simulations to the most informative corners, thus minimizing redundancy in multicorner characterization. Evaluated on industrial 22nm standard cells across 16 PVT corners, SetupKit demonstrates a significant 2.4x overall CPU time reduction (from 720 to 290 days on a single core) compared to standard practices, drastically cutting characterization time. SetupKit offers a principled, learningbased approach to library characterization, addressing a critical EDA challenge and paving the way for more intelligent simulation management.

Figures (10)

• Figure 1: Waveform behavior for different setup skews.
• Figure 2: CK-Q delay behavior for different setup skews.
• Figure 3: Test points obtained from different search methods. Given root's Y location threshold; two interval endpoints P$_1$ and P$_2$; outside adjacent point P$_3$.
• Figure 4: Above: quadratic interpolation. Bottom: finding the bias $\varepsilon$ from the distribution of $x_0$, assuming the estimation error is under Gaussian distribution.
• Figure 5: As uncertainty ($\sigma$) increases from 0.001 to 100, BEIRA smoothly transitions from interpolation-based test points to bisection-like behavior ($x_0'=0.1$, $\beta=5$, for $n = 0,...,7$).