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Architect in the Loop Agentic Hardware Design and Verification

Mubarek Mohammed

TL;DR

The paper addresses rising hardware design complexity by proposing a blueprint-driven agentic design workflow with an architect-in-the-loop. It uses JSON blueprints, iterative HDL/testbench generation, linting, cocotb verification, and a self-correction loop to assemble and verify processors (LEGv8-like and a 32-bit RISC-V-like) on FPGA. It identifies the semantic cohesion gap as a key limitation and documents debugging experiences and concrete fixes. It concludes that AI can dramatically reduce cost and time, but requires human oversight to ensure design intent and system-level correctness, paving the way for scalable Architect-in-the-Loop workflows.

Abstract

The ever increasing complexity of the hardware design process demands improved hardware design and verification methodologies. With the advent of generative AI various attempts have been made to automate parts of the design and verification process. Large language models (LLMs) as well as specialized models generate hdl and testbenches for small components, having a few leaf level components. However, there are only a few attempts to automate the entire processor design process. Hardware design demands hierarchical and modular design processes. We utilized this best practice systematically and effectively. We propose agentic automated processor design and verification with engineers in the loop. The agent with optional specification tries to break down the design into sub-components, generate HDL and cocotb tests, and verifies the components involving engineer guidance, especially during debugging and synthesis. We designed various digital systems using this approach. However, we selected two simple processors for demonstration purposes in this work. The first one is a LEGv8 like a simple processor verified, synthesized and programmed for the DE-10 Lite FPGA. The second one is a RISC-V like 32-bit processor designed and verified in similar manner and synthesized. However, it is not programmed into the DE-10 Lite. This process is accomplished usually using around a million inference tokens per processor, using a combination of reasoning (e.g gemini-pro) and non-reasoning models (eg. gpt-5-mini) based on the complexity of the task. This indicates that hardware design and verification experimentation can be done cost effectively without using any specialized hardware. The approach is scalable, we even attempted system-on-chip, which we want to experiment in our future work.

Architect in the Loop Agentic Hardware Design and Verification

TL;DR

The paper addresses rising hardware design complexity by proposing a blueprint-driven agentic design workflow with an architect-in-the-loop. It uses JSON blueprints, iterative HDL/testbench generation, linting, cocotb verification, and a self-correction loop to assemble and verify processors (LEGv8-like and a 32-bit RISC-V-like) on FPGA. It identifies the semantic cohesion gap as a key limitation and documents debugging experiences and concrete fixes. It concludes that AI can dramatically reduce cost and time, but requires human oversight to ensure design intent and system-level correctness, paving the way for scalable Architect-in-the-Loop workflows.

Abstract

The ever increasing complexity of the hardware design process demands improved hardware design and verification methodologies. With the advent of generative AI various attempts have been made to automate parts of the design and verification process. Large language models (LLMs) as well as specialized models generate hdl and testbenches for small components, having a few leaf level components. However, there are only a few attempts to automate the entire processor design process. Hardware design demands hierarchical and modular design processes. We utilized this best practice systematically and effectively. We propose agentic automated processor design and verification with engineers in the loop. The agent with optional specification tries to break down the design into sub-components, generate HDL and cocotb tests, and verifies the components involving engineer guidance, especially during debugging and synthesis. We designed various digital systems using this approach. However, we selected two simple processors for demonstration purposes in this work. The first one is a LEGv8 like a simple processor verified, synthesized and programmed for the DE-10 Lite FPGA. The second one is a RISC-V like 32-bit processor designed and verified in similar manner and synthesized. However, it is not programmed into the DE-10 Lite. This process is accomplished usually using around a million inference tokens per processor, using a combination of reasoning (e.g gemini-pro) and non-reasoning models (eg. gpt-5-mini) based on the complexity of the task. This indicates that hardware design and verification experimentation can be done cost effectively without using any specialized hardware. The approach is scalable, we even attempted system-on-chip, which we want to experiment in our future work.

Paper Structure

This paper contains 22 sections, 2 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. Verilog Generation and Evaluation
  4. AI Assisted Digital Systems Design
  5. The AI-Driven Design Methodology
  6. Phase 1: The Blueprint as a Formal Specification
  7. Phase 2: Component Generation, Integration, and Self-Correction
  8. Phase 3: System-Level Verification
  9. Debugging and Root Cause Analysis
  10. Analysis of Agentic Capabilities and Limitations
  11. Strengths
  12. Limitations: The Semantic Cohesion Gap
  13. Economic and Future Implications
  14. A Highly Cost-Effective Collaboration
  15. The Path Forward: The Architect-in-the-Loop
  16. ...and 7 more sections

Figures (2)

  • Figure 1: Agentic Digital Design Flow with Human-in-the- Loop Feedback and Approval at Each Stage
  • Figure 2: Refined Agentic Digital Design Flow with Human-in-the- Loop