VeriPy -- A New Python-Based Approach for SDR Pipelined/Unrolled Hardware Accelerator Generation

TL;DR

VeriPy presents a Python-based SDR-specific HLS tool that automatically generates unrolled and pipelined Verilog from Python algorithms, with automatic testbench generation, an extensible hardware library, and performance/resource estimation. It employs a one-to-one mapping between Python functions and hardware modules using a binary-tree IR, enabling synthesizable Verilog with improved readability and reuse. Evaluation across SDR benchmarks shows VeriPy can reach up to 1.7× the frequency of pragma-optimised Vivado HLS designs, with resource usage comparable to hand-coded Verilog, illustrating a practical trade-off between ease-of-use and hardware efficiency. The framework lowers the barrier for SDR engineers to leverage FPGA accelerators, while offering pathways for further optimization and library expansion.

Abstract

Software-defined radio (SDR) plays an important role in the communication field by providing a flexible and customized communication system for different purposes according to the needs. To enhance the performance of SDR applications, hardware accelerators have been widely deployed in recent years. In facing this obstacle, a necessity arises for a high-level synthesis (HLS) tool specifically designed for communication engineers without detailed hardware knowledge. To lower the barrier between SDR engineers and hardware development, this work proposed a Python-based HLS tool, VeriPy, which can generate both mainstream architecture for hardware accelerators in Verilog specifically for SDR designs including unrolled design and pipelined design, requiring no detailed digital hardware knowledge or Hardware Description Languages (HDL). Furthermore, VeriPy supports automatic testbench generation with random input stimulus, an extensible hardware library, performance and resource estimation, and offers strong optimisation potential at both the algorithmic and digital hardware levels. The generated hardware design by VeriPy can achieve up to 70% faster operating frequency compared to pragma-optimised Vivado HLS designs with a reasonably higher resource con-sumption while delivering comparable performance and resource consumption to hand-coded implementations. Regarding code complexity, VeriPy requires no pragmas, completely eliminating the need for low-level hardware knowledge. For straightforward algorithms, the input code length remains comparable to that of Vivado HLS.

Figures (13)

• Figure 1: Tool structure.
• Figure 2: The Design Flow Comparison between Vivado HLS and VeriPy.
• Figure 3: Comparison of the Input Code between HLS and VeriPy.
• Figure 4: Hardware Architecture of the Provided Fundamental Functions.
• Figure 5: