ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction

TL;DR

This work tackles the challenge of predicting layout-level PPA metrics from netlists for unseen, large-scale circuits. It introduces ParaGate, a three-step framework that first learns parasitic parameters via a two-phase transfer-learning scheme, then leverages EDA tools for long-path timing/power reasoning, and finally applies subgraph-based calibration to refine predictions. The approach demonstrates strong generalization with minimal fine-tuning, notably boosting openE906 arrival-time $R^2$ from 0.119 to 0.897 and achieving low power-relative errors on diverse designs. By decoupling parasitic learning from global timing/power analysis and incorporating global information, ParaGate enables earlier, more reliable guidance for synthesis and placement optimization in modern VLSI design flows.

Abstract

In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-network-based solutions predict layout-level performance directly from netlists, they often face generalization challenges due to the black-box heuristics of commercial placement-and-routing tools, which create disparate data across designs. To this end, we propose ParaGate, a three-step cross-stage prediction framework that infers layout-level timing and power from netlists. First, we propose a two-phase transfer-learning approach to predict parasitic parameters, pre-training on mid-scale circuits and fine-tuning on larger ones to capture extreme conditions. Next, we rely on EDA tools for timing analysis, offloading the long-path numerical reasoning. Finally, ParaGate performs global calibration using subgraph features. Experiments show that ParaGate achieves strong generalization with minimal fine-tuning data: on openE906, its arrival-time R2 from 0.119 to 0.897. These results demonstrate that ParaGate could provide guidance for global optimization in the synthesis and placement stages.

Figures (6)

• Figure 1: (a) End-to-end method lacking generalizability; (b) Potential task coupling in PPA prediction
• Figure 2: ParaGate framework.
• Figure 3: Generation of PinGraph features and label.
• Figure 4: Overall Performance of ParaGate and Comparisons.
• Figure 5: ParaGate ablation study.