VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization

TL;DR

VeriDispatcher tackles the challenge of coordinating multiple LLMs for RTL generation by predicting model-specific task difficulty from semantic embeddings. It trains per-model predictors to decide which LLM should handle each RTL task and supports top-k dispatching and budget-aware configurations. The approach achieves up to 18.18% accuracy gains on RTLLM and 5.77% on VerilogEval while reducing commercial usage, illustrating cost-effective deployment. The work highlights the importance of model-dependent difficulty signals and semantic richness in embeddings for effective multi-LLM collaboration in hardware design automation.

Abstract

Large Language Models (LLMs) show strong performance in RTL generation, but different models excel on different tasks because of architecture and training differences. Prior work mainly prompts or finetunes a single model. What remains not well studied is how to coordinate multiple different LLMs so they jointly improve RTL quality while also reducing cost, instead of running all models and choosing the best output. We define this as the multi-LLM RTL generation problem. We propose VeriDispatcher, a multi-LLM RTL generation framework that dispatches each RTL task to suitable LLMs based on pre-inference difficulty prediction. For each model, we train a compact classifier over semantic embeddings of task descriptions, using difficulty scores derived from benchmark variants that combine syntax, structural similarity, and functional correctness. At inference, VeriDispatcher uses these predictors to route tasks to a selected subset of LLMs. Across 10 diverse LLMs on RTLLM and VerilogEval, VeriDispatcher achieves up to 18% accuracy improvement on RTLLM using only 40% of commercial calls, and on VerilogEval maintains accuracy while reducing commercial usage by 25%, enabling cost-effective, high-quality LLM deployment in hardware design automation.

Figures (6)

• Figure 1: Traditional multi-LLM RTL generation vs. difficulty-aware VeriDispatcher.
• Figure 2: Complete VeriDispatcher pipeline from task embedding extraction through difficulty-aware model dispatching.
• Figure 3: Classifier F1-macro scores on VerilogEval benchmark comparing embedding strategies and classifier architectures.
• Figure 4: Classifier F1-macro scores on RTLLM benchmark comparing embedding strategies and classifier architectures.
• Figure 5: Number of solved cases across Top-K dispatching strategies for VerilogEval and RTLLM benchmarks.