Deep-Cryogenic Modeling of 22-nm FDSOI MOSFETs based on BSIM-IMG

TL;DR

The paper addresses the need for accurate deep-cryogenic transistor models in cryo-CMOS by introducing a deep-cryogenic modeling flow for 22-nm FDSOI MOSFETs based on a modified BSIM-IMG. It combines DC-based static parameter extraction with RF-based dynamic parameter extraction and incorporates a new intersubband scattering mobility term to capture cryogenic-specific behavior. The methodology is validated through extraction from large test arrays and a cryogenic current-output DAC demonstration, showing close agreement with measurements and quantifying variability effects via Monte Carlo analysis. While the approach advances predictive capabilities at deep cryogenic temperatures, it relies on an isothermal assumption and points to future work on noise, layout effects, parasitics, and subthreshold oscillations to broaden applicability.

Abstract

We present a modeling approach based on the BSIM-IMG compact model to capture the deep-cryogenic behavior of MOSFET devices in a 22-nm FDSOI technology. The modeling flow is based on DC measurements to extract static parameters including variability and RF measurements to extract dynamic parameters. Modifications to the mobility equations are introduced to enable the modeling of intersubband scattering effect. The extracted models are used to enable deep-cryogenic simulations of a digital-to-analog converter (DAC), showing close agreement with measurement results.

Figures (10)

• Figure 1: MOSFET model card parameter extraction flow incorporating DC (left) and RF (right) sub-flows.
• Figure 2: DC $I_\mathrm{d}-V_\mathrm{gs}$ sweeps at $\sim$15 mK ambient temperature in the linear region ($V_\textrm{ds}=50$ mV) for four corner device geometries of: (a) thin-oxide n-type MOSFETs; (b) thin-oxide p-type MOSFETs; (c) thick-oxide n-type MOSFETs; and (d) thick-oxide p-type MOSFETs. Solid lines and circles correspond to typical simulated and measured drain current values, respectively.
• Figure 3: DC $I_\mathrm{d}-V_\mathrm{gs}$ sweeps at $\sim$15 mK ambient temperature for thin-oxide n-type MOSFETs. Solid lines and circles correspond to typical simulated and measured drain current values, respectively. (a) Effect of drain bias for a short/moderate-width device geometry. (b) Effect of back-gate bias for a wide/long device geometry in the linear region ($V_\mathrm{ds}=50$ mV). (c,d) Effect of channel length for constant-width (wide) device geometries in the (c) linear region ($V_\mathrm{ds} = 50$ mV); and (d) saturation region ($V_{ds} = 800$ mV). Insets: $V_\mathrm{th}$ vs. normalized channel length.
• Figure 4: Linear region $I_\mathrm{d}-V_\mathrm{gs}$ sweeps of a thick-oxide n-type narrow/long device geometry under different back-gate bias conditions. Mobility degradation due to intersubband scattering can be observed for higher back-gate bias voltage. The inset plot shows the corresponding calculated DC trans-conductance ($g_\mathrm{m}$) vs. $V_\mathrm{gs}$.
• Figure 5: Extracted $USS$ and $ESS0$ parameter values for different geometries of thick-oxide n-type MOSFETs.