No need to calibrate: characterization and compilation for high-fidelity circuit execution using imperfect gates
Ashish Kakkar, Samuel Marsh, Yulun Wang, Pranav Mundada, Paul Coote, Gavin Hartnett, Michael J. Biercuk, Yuval Baum
TL;DR
The study tackles the bottleneck of calibrating two-qubit entangling gates by proposing a characterize-and-compile pipeline that learns a small set of gate parameters from fast tomography and encodes their nonlocal content in Weyl chamber coordinates (c1,c2,c3). A hardware-agnostic workflow then synthesizes target unitaries from an extended gate set using the Cartan decomposition, supported by a coverage-set/invariant framework and accelerated routines for controlled and single-axis pulses. Key contributions include an end-to-end pipeline for extended gate-set construction and synthesis, practical acceleration strategies, and IBM-device demonstrations showing up to 7x improvements in QFT success probability and up to 9x reductions in MSE for TFIM simulations. The approach reduces calibration overhead and enables scalable, high-fidelity circuit execution across architectures, with potential extensions to drift-robust characterization and multi-axis controls for broader platforms.
Abstract
We propose and validate on real quantum computing hardware a new method for extended two-qubit gate set design, replacing iterative, fine calibration with fast characterization of a small number of gate parameters which are then tracked and corrected in circuit compilation. Coherent contributions to the pulse unitary that would traditionally be considered sources of error are treated as part of the gate definition, and compensated in software via single-qubit rotations. This approach enables rapid device-wide generation of high-fidelity two-qubit entangling gates, which are combined with standard calibrated gates to produce an expanded gate set. We show how these gates are directly usable as part of a quantum compiler, synthesizing generic two-qubit circuit blocks into minimal-duration sequences of the characterized gates interleaved with compensating single-qubit rotations. Benchmarking against circuits compiled using the default $CX$ gate alone on 127-qubit IBM hardware shows up to 7X improvement in success probability for Quantum Fourier Transform circuits up to 26 qubits, and up to 9X lower mean-square error in Trotter simulations of the one-dimensional transverse-field Ising model. Our hardware-agnostic characterization and compilation methodology makes it practical to scale up expressive gate sets on quantum computing architectures while minimizing the need for onerous fine-tuning of low-level control waveforms.
