Sneak Path Current Modeling in Memristor Crossbar Arrays for Analog In-Memory Computing

TL;DR

This work tackles sneak-path currents in passive memristor crossbar arrays used for analog in-memory computing by introducing a closed-form analytical framework based on IMEC A14 interconnects. The model captures the joint influence of array size, memristor ON/OFF ratio, read voltage, data patterns, and interconnect conditions, yielding $I_{sneak}$ with less than 10.9% error and up to 4784x faster runtime than SPICE. It provides a comprehensive sensitivity analysis and demonstrates strong validation against circuit simulations, offering a practical tool for pre-design and real-time optimization of large-scale memristor-based IMC architectures. The approach enables rapid exploration of design trade-offs to balance scalability, noise margins, and energy efficiency in analog crossbar systems.

Abstract

Memristor crossbar arrays have emerged as a key component for next-generation non-volatile memories, artificial neural networks, and analog in-memory computing (IMC) systems. By minimizing data transfer between the processor and memory, they offer substantial energy savings. However, a major design challenge in memristor crossbar arrays is the presence of sneak path currents, which degrade electrical performance, reduce noise margins, and limit reliable operations. This work presents a closed-form analytical framework based on IMEC A14 (1.4 nm) Technology for accurately estimating sneak path currents in memristor crossbar arrays. The proposed model captures the interdependence of key design parameters in memristor crossbar arrays, including array size, ON/OFF ratio of memristors, read voltage, and interconnect conditions, through mathematically derived relationships. It supports various practical configurations, such as different data patterns and connection strategies, enabling rapid and comprehensive sneak path current modeling. The sensitivity analysis includes how design parameters influence sneak path current and noise margin loss, underscoring the trade-offs involved in scaling crossbar arrays. Validation through SPICE simulations shows that the model achieves an error of less than 10.9% while being up to 4784 times faster than full circuit simulations. This analytical framework offers a powerful tool for quantitative assessment and pre-design/real-time optimization of memristor-based analog in-memory computing (IMC) architectures.

Figures (7)

• Figure 1: (a) Structure of the linear dopant drift memristor model. h represents the total thickness of the device. w represents the thickness of the doped region; (d) Current versus voltage characteristic for the memristor robinett2007demultiplexers. A $3 \times 3$ memristive crossbar, where Vdd = V2 is the voltage applied in row 2, and current sensed from column 2: (b) the crossbar without sneak paths where the desired current path is marked in green line, (c) presence of a sneak path which is marked in red line, (e) FRC connection strategy with 'All Ones' (LRS) data pattern, (f) GRC connection strategy with 'All Zeros' (HRS) data pattern. Here, in GRC connection strategy, shorted row nodes are indicated as "nrs" and shorted column nodes are indicated as "ncs".
• Figure 2: (a) Metal layers M1 M12 are used for interconnect within the cell; (b) Sketch of Cu for interconnect material; (c) Top view of a unit-cell memristor crossbar array for M5/M4 with IMEC A14.
• Figure 3: Simulation results for sneak path current in terms of array sizes, data patterns ('All Zeros' and 'All Ones'), FRC connection strategy, and line resistance M3 (Rline = $3.122\,\Omega$) where the read voltages are incremented along the rows and ON/OFF ratio is incremented along the columns of the subplots. The rise in sneak path current with respect to the increment of the ON/OFF ratio along the columns as Kon = [1e-9, 3e-8, 5e-8, 8e-8, 1e-7] for a specific read voltage: (a e) Vdd = 1.0 V; (f j) Vdd = 1.5 V; (k o) Vdd = 2.0 V; (p t) Vdd = 2.5 V; (u y) Vdd = 3 V. Noticeably, for 'All Ones' pattern the sneak path current increases rapidly for the increments of read voltage, ON/OFF ratio, array size compared to the minimal increment of All Zeros data pattern.
• Figure 4: Simulation results for noise margin versus array sizes, data patterns ('All Zeros' and 'All Ones'), FRC connection strategy, and line resistance M3 (Rline = $3.122\,\Omega$) where the read voltages are incremented along the rows and ON/OFF ratio is incremented along the columns of the subplots. The fall of noise margin for 'All Ones' data pattern with respect to the increment of the ON/OFF ratio along the columns as Kon = [1e-9, 3e-8, 5e-8, 8e-8, 1e-7] for a specific read voltage: (a e) Vdd = 1.0 V; (f j) Vdd = 1.5 V; (k o) Vdd = 2.0 V; (p t) Vdd = 2.5 V; (u y) Vdd = 3 V. Noticeably, for 'All Ones' pattern, noise margin rapidly decreases with respect to the increments of read voltage, ON/OFF ratio, array size compared to approximately zero decrease for 'All Zeros' data pattern.
• Figure 5: (a) Sneak path current and (b) noise margin of the target cell versus array size for the interconnect layers using the IMEC A14 technology node. The array adopts ‘All Ones’ data pattern with FRC connection strategy. Kon is 1e-7. Vdd is 3 V.