A 0.32 mm$^2$ 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection

TL;DR

This work addresses the challenge of reliable wireless reception under smart and barrage jamming by introducing MAED, a joint estimation and detection framework that unifies jammer mitigation, channel estimation, and data detection for an 8×1 SIMO system. The MAED algorithm is hardware-oriented, employing alternating optimization and proximal operations, with rearrangements that replace matrix-matrix operations by matrix-vector products and exploit fixed-point-friendly scaling. The authors implement MAED as a 22 nm FD-SOI ASIC (core area 0.32 mm^2) that achieves 100 Mb/s at 223 mW, delivering 314 Mb/s/mm^2 area efficiency and 2.2 nJ/b energy even under strong jamming (ρ = 30 dB), and it outperforms prior jammer-resilient detectors in both BER and hardware efficiency. These results demonstrate the practicality of silicon-proven, joint jammer mitigation and data detection for real-time, energy-aware, jammed-SIMO links in hostile environments.

Abstract

We present the first single-input multiple-output (SIMO) receiver ASIC that jointly performs jammer mitigation, channel estimation, and data detection. The ASIC implements a recent algorithm called siMultaneous mitigAtion, Estimation, and Detection (MAED). MAED mitigates smart jammers via spatial filtering using a nonlinear optimization problem that unifies jammer estimation and nulling, channel estimation, and data detection to achieve state-of-the-art error-rate performance under jamming. The design supports eight receive antennas and enables mitigation of smart jammers as well as of barrage jammers. The ASIC is fabricated in 22 nm FD-SOI, has a core area of 0.32 mm$^2$, and achieves a throughput of 100 Mb/s at 223 mW, thus delivering 3$\times$ higher per-user throughput and 4.5$\times$ higher area efficiency than the state-of-the-art jammer-resilient detector.

Figures (8)

• Figure 1: Considered scenario of a SIMO uplink attacked by a (smart) jammer.
• Figure 2: Top view of the MAED architecture with zoom-in on the architecture of the processing elements (PEs). The bitwidths shown for registers and flip-flop (FF) arrays are per real and imaginary part of variables.
• Figure 3: Cannon's algorithm and its Hermitian variant illustrated for a $3\times 3$ matrix-vector product: (a) To compute $\mathbf{A}\xspace\mathbf{x}\xspace$, the $j$th PE stores $\mathbf{a}\xspace_j$, the $j$th row of matrix $\mathbf{A}\xspace$. Each PE starts with $x_k$ and multiplies it by $a_{j,k}$. The PEs then circularly exchange the entries of $\mathbf{x}\xspace$ and accumulate the partial products until completing $\mathbf{A}\xspace\mathbf{x}\xspace$. (b) In the Hermitian variant, the PEs compute $\mathbf{A}\xspace^{H}\mathbf{z}\xspace$ by circularly exchanging the accumulated partial products while keeping the entries of $\mathbf{z}\xspace$ fixed. The entries of $\mathbf{a}\xspace_j$ are read in the same order as for $\mathbf{A}\xspace\mathbf{x}\xspace$.
• Figure 4: Modules of the MAED architecture.
• Figure 5: Uncoded bit error-rate (BER) of different SIMO receivers as a function of the SNR for different jamming scenarios (cf. sec:model). The receive jammer-to-signal ratio of all jammers is equal to $\rho=30$ dB.