A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm

TL;DR

This work addresses the challenge of time synchronization in the presence of smart jamming by implementing the Jammer-Aware SynchroniSation (JASS) algorithm on an ASIC. The design uses a 16-antenna receiver and up to 2-jammer antennas, applying interference-subspace projections and a programmable threshold to detect the start of a synchronization sequence within a windowed observation $\mathbf{Y}_\ell$. The resulting JASS ASIC in 65 nm CMOS (core area $2.87$ mm$^2$) operates at up to $344$ MHz to deliver $1.28$ MS/s, drawing $310$ mW, and demonstrates robust performance across jammer types with fixed-point accuracy close to floating-point. This enables jammer-resilient synchronization for uplink scenarios and motivates further scaling via parallelism or advanced nodes for higher rates, at the expense of area and power. The work represents the first open-literature ASIC realization of a jammer-resilient synchronization method and provides concrete hardware-friendly primitives such as PRNG, $\|\cdot\|_{\hat{\infty}}$-pseudonormalization, and an inverse-square-root module to support real-time operation.

Abstract

We present the first ASIC implementation of jammer-resilient multi-antenna time synchronization. The ASIC implements a recent algorithm that mitigates jamming attacks on synchronization signals using multi-antenna processing. Our design supports synchronization between a single-antenna transmitter and a 16-antenna receiver while mitigating smart jammers with up to two transmit antennas. The fabricated 65 nm ASIC has a core area of 2.87 mm$^2$, consumes a power of 310 mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s).

Figures (6)

• Figure 1: Overview of the JASS architecture, consisting of 16 reconfigurable processing elements (PEs), a pseudorandom number generator (PRNG), a $\|{\cdot}\|_{\hat{\infty}}$--pseudonormalization (PN) module, an inverse square root module, and the score module. Blocks in green correspond to flip-flops (FFs) and FF arrays. The $\bilambdad\xspace^{T}_{n}$ and $\biphid\xspace^{T}_{n}$ FF arrays store the $n$th row of $\biLambda$ and $\biPhi$, respectively.
• Figure 2: Illustration of three different PE configurations for the execution of the operations of the JASS algorithm.
• Figure 3: Internal structure of the (a) PRNG module, (b) $\|{\cdot}\|_{\hat{\infty}}$--PN module, and (c) inverse square root module of the JASS hardware architecture.
• Figure 4: Synchronization error rate (SER) performance against a two-antenna jammer at a signal-to-noise ratio (SNR) of $5$ dB, for different jammer types and jammer-to-signal ratios $\rho$. The delayed-spoofing jammer repeats the synchronization sequence $\breve\mathbf{s}\xspace$ with one sample delay; the antenna-switching jammer transmits Gaussian symbols using sometimes one antenna, sometimes the other; the erratic jammer transmits Gaussian symbols at random times and is otherwise silent; and the barrage jammer transmits white Gaussian noise.
• Figure 5: Micrograph of the $2\,\text{mm}\times2\,\text{mm}$ JASS ASIC in TSMC 65 nm LP with highlighted modules.