Multiport Analytical Pixel Electromagnetic Simulator (MAPES) for AI-assisted RFIC and Microwave Circuit Design

TL;DR

MAPES delivers a physics-based, analytical multiport framework for fast EM prediction of arbitrary pixel-based MW/RFIC structures by converting the design into a virtual-pixel network with diagonal virtual pixels and a single impedance matrix. A small set of full-wave simulations builds the prior matrix $oldsymbol{Z}_{ALL}$, after which any pixel pattern is evaluated via a closed-form formula to yield S-parameters, enabling 600–2000× speedups with high fidelity across CMOS and PCB cases. This approach avoids data-driven overfitting inherent to AI surrogates, scales to multi-layer and via-containing designs, and offers practical use as a fast dataset generator and physics-informed backbone for inverse design and RL-based layout optimization. Comparisons with CST show excellent agreement, while the method provides substantial reductions in data and computation, making it attractive for AI-assisted RFIC/microwave circuit design.

Abstract

This paper proposes a novel analytical framework, termed the Multiport Analytical Pixel Electromagnetic Simulator (MAPES). MAPES enables efficient and accurate prediction of the electromagnetic (EM) performance of arbitrary pixel-based microwave (MW) and RFIC structures. Inspired by the Integrated Internal Multiport Method (IMPM), MAPES extends the concept to the pixel presence/absence domain used in AI-assisted EM design. By introducing virtual pixels and diagonal virtual pixels and inserting virtual ports at critical positions, MAPES captures all horizontal, vertical, and diagonal electromagnetic couplings within a single multiport impedance matrix. Only a small set of full-wave simulations (typically about 1% of the datasets required by AI-assisted EM simulators) is needed to construct this matrix. Subsequently, any arbitrary pixel configuration can be evaluated analytically using a closed-form multiport relation without additional full-wave calculations. The proposed approach eliminates data-driven overfitting and ensures accurate results across all design variations. Comprehensive examples for single- and double-layer CMOS processes (180 nm and 65 nm) and PCBs confirm that MAPES achieves high prediction accuracy with 600- 2000x speed improvement compared to CST simulations. Owing to its efficiency, scalability and reliability, MAPES provides a practical and versatile tool for AI-assisted MW circuit and RFIC design across diverse fabrication technologies.

Figures (18)

• Figure 1: Overview of the MAPES methodology detailing the calculation process (top row) and the equivalent model of MAPES (bottom row). (a) The pixel-based design space is defined by the pixel occupancy matrix $\mathbf{P}$ whose binary entries model the presence (1) or absence (0) of pixels; (b) map the design space $\mathbf{P}$ to the virtual port load matrix using the proposed mapping algorithm; (c) analytically predict performance at the chosen I/O ports via the closed-form multiport method; (d) the equivalent model of the design space $\mathbf{P}$ is created using virtual pixels and inserting diagonal virtual pixels at pixel corners; (e) insert virtual ports between adjacent virtual pixels and diagonal virtual pixels; (f) perform full-wave simulations (e.g., CST, HFSS) to extract the impedance matrix capturing all key electromagnetic effects of the equivalent model.
• Figure 2: Magnified view of the design space (left) and the equivalent model (right). The model (right) consists of virtual pixels and diagonal virtual pixels in MAPES.
• Figure 3: Magnified view of the virtual pixel structure (left) and the insertion of virtual ports (right), including horizontal, vertical and diagonal virtual ports in the MAPS methodology.
• Figure 4: Two representative examples of how the design space pixel patterns are mapped to the equivalent model in MAPES methodology.
• Figure 5: Model of the multiport network for analytical calculation in the MAPES methodology. The connections between virtual pixels are modelled by the loads specified by $Z_L$ on the left side. The MAPES calculation process uses $Z_L$ with the Z matrix (middle) to determine the Z- or S-parameters of the I/O ports (right).