Defect-Aware Physics-Based Compact Model for Ferroelectric nvCap: From TCAD Calibration to Circuit Co-Design

TL;DR

This work introduces a physics-based compact model for ferroelectric nvCap that accounts for small-signal capacitance, interface and bulk defects, and device variability, all calibrated against TCAD and experimental data. By integrating a defect-aware leakage mechanism and polarization screening into a VerilogA framework, the method enables material–device–circuit co-design and validates read operation in selector-less, crossbar-like memories with aging considerations. The approach delivers sub-5 mV read margins under realistic variability and aging scenarios, offering design guidelines for robust, high-density non-volatile memory and compute-in-memory implementations. Overall, the framework connects process conditions and defect evolution to circuit-level performance, enabling reliable, scalable NVCap-based memory designs from TCAD calibration to circuit co-design.

Abstract

Ferroelectric non-volatile capacitance-based memories enable non-destructive readout and low-power in-memory computing with 3D stacking potential. However, their limited memory window (1-10 fF/μm) requires material-device-circuit co-optimization. Existing compact models fail to capture the physics of small-signal capacitance, device variability, and cycling degradation, which are critical parameters for circuit design. In non-volatile capacitance devices, the small-signal capacitance difference of the polarization states is the key metric. The majority of the reported compact models do not incorporate any physical model of the capacitance as a function of voltage and polarization. We present a physics-based compact model that captures small-signal capacitance, interface and bulk defect contributions, and device variations through multi-scale modeling combining experimental data, TCAD simulations, and circuit validation. Based on this methodology, we show optimized memory read-out with +/- 5 mV sense margin and impact of device endurance at the circuit level. This work presents a comprehensive compact model which enables the design of selector-less arrays and 3D-stacked memories for compute-in-memory and storage memory.

Figures (9)

• Figure 1: (a) Illustration of the nvCap capacitance and polarization hysteresis. A capacitive memory window $\Delta C$ can be extracted as difference between the and the . (b) Possible application in a selector-less crossbar array enabled by the capacitive nature of the memory device.
• Figure 2: (a) Material stack of the fabricated nvCap devices. (b) The nvCap device behavior is impacted by non-idealities, such as the carrier density at the electrode interface leading to finite screening, bulk traps in the HZO causing leakage currents and interface traps that screen the polarization, circumventing depolarization effects from finite screening due to the electrode depletion and interface layer. (c) Equivalent circuit that models the ferroelectric switching and its interaction with the depletion effect, interface layer and leakage currents self-consistently. (d) Calibration flow with the parameters extracted in each step. The calibration is based on technology data, electrical characterization data and TCAD simulations, leading to a physics-based VerilogA compact model that enables material-device-circuit co-design by circuit validation and design feedback.
• Figure 3: (a) Capacitance vs Voltage curve using quasi-static voltage sweep after 1000 wake-up cycles and compact model fit with the experimental curve. (b) Polarization vs Voltage curve after 1000 wake-up cycles using PUND sequence of 1 kHz and fit of the compact model with the experimental curve. (c) Compact model simulation of the switching kinetics towards the down polarization state showing the transient programming behavior.
• Figure 4: (a) Capacitance vs Cycles measured using quasi-static voltage sweep from 0 V to 200 mV after every 1000 cycles. (b) Erasing obtained by applying incrementally positive polarity pulse amplitudes, capacitance measured at DC 0 V and 0.2 V, and fit of the compact model with the experimental curve.
• Figure 5: (a) Capacitance measured at 0 V over cycles (crosses) and compact model Monte Carlo simulation of the LCS and HCS capacitance with mean and 3 $\mathrm{\sigma}$. (b) Compact model Monte Carlo simulation of the capacitance hysteresis with mean and 3 $\mathrm{\sigma}$ indicated. (c) Programming curve of the HCS, measured at 0 V, and the respective compact model Monte Carlo simulation with mean and 3 $\mathrm{\sigma}$.