Planar Josephson junctions for sensors and electronics:Different geometry, new functionality

Abstract

Josephson junctions are key elements in superconducting electronics. The most common type is the overlap (sandwich-type) junction, formed by vertically stacking two superconducting layers. In contrast, planar junctions are fabricated without overlap, at the edge of two superconducting films within a single plane. This geometric distinction has a significant impact on their physical properties. The planar geometry greatly enhances sensitivity to magnetic fields and improves impedance matching for terahertz (THz) devices. Its two-dimensional structure allows for simple and flexible electronic component design, enabling drastic miniaturization. Here I highlight recent advances in the application of planar junctions for novel technologies, including junction-on-cantilever sensors for super-resolution magnetic imaging, vortex-based memory cells, and programmable superconducting diodes. I will also discuss the general requirements, future perspectives, and key challenges in the evolving field of superconducting electronics.

Figures (4)

• Figure 1: (a) A sketch of geometry difference between overlap and planar Josephson junctions. (b) A sketch of planar junction fabrication by focused ion beam. (c) SEM image of a scanning probe sensor with a Nb/CuNi/Nb planar junction on a cantilever. (d) SEM image of a planar Nb/CuNi/Nb junction with a vortex trap in one electrode. (e) measured $I_c(H)$ characteristics of the junction from (d) in the Meissner state (blue) and with a trapped antivortex (red). (f) Holographic reconstruction of vortex stray field in the junction using the distorted (red) $I_c(H)$ pattern from (e) as a hologram. The inset shows the difference between the actual and reconstructed field profiles. The accuracy of reconstruction $\sim 20$ nm is much smaller than the junction length $L_x~\sim 5~\mu$m, which indicates super-resolution imaging. Panels (a), (b) and (c-f) were adopted from Refs. Boris_2013, Krasnov_2005 and Hovhannisyan_2023, respectively.
• Figure 2: (a) SEM image (false color) of an array with nine variable-thickness bridge type planar Nb junctions, and with additional electrodes to intermediate electrodes 2 and 5. (b) Current - Voltage characteristics of the three array segments, normalized by the number of JJs in the segment. Coincidence of the curves indicates the reproducibility of the fabrication technique and perfect current-locking of all JJs. (c) Temperature dependence of $I_c R_n$ for two arrays with three and nine JJs. Adopted from Ref. Grebenchuk_2022.
• Figure 3: A sketch (top) and a SEM image (bottom) of a four-terminal Josephson diode with a vortex trap. (b) Magnetic field modulation of critical current in the absence of vortex for three bias configurations sketched in (a). The asymmetric corner bias leads to a profound nonreciprocity at finite magnetic field. (c) $I_c(H)$ modulation for the right-corner bias with a trapped vortex. Note that the largest nonreciprocity is shifted to zero field. The diode polarity of such a diode is switchable by changing the sign of trapped vortex and the bias configuration. Adopted from Ref. Golod_2022.
• Figure 4: (a) SEM image (false color) of a $\sim 1\times 1~\mu$m$^2$ vortex-based AVRAM memory cell. (b) Demonstration of write and erase operation by word-line (red) and bit-line (blue) current pulses. The top panel shows current pulse sequence. The bottom panel represents the resistance of readout JJ. (c) Demonstration of a long-time fault free operation for another device. (d-f) TDGL modeling of cell operation. (d) Cell geometry with spatial distribution of the order parameter (left) and current density (right). The width of the electrode is $1~\mu$m, as in (a). (e) Average vortex velocities along the path from the right to the left edge at three bias currents. (f) Demonstration of ultrafast write/erase operation by bipolar current pulses. Panels (a,b), (c) and (d-f) are adopted from Refs. Golod_2023, Golod_2015 and Skog_2024, respectively.