Device-Scale Atomistic Simulations of Heat Transport in Advanced Field-Effect Transistors

TL;DR

This work presents NEP-FET, a framework that unites near-quantum-accuracy atomistic modeling with device-scale throughput to study heat transport in advanced transistors. By training a neuroevolution potential on an expanded, interface-rich dataset and coupling it to the FETMOD geometry generator, NEP-FET enables fully atomistic simulations of multi-million-atom transistor structures and outputs spatially resolved temperature fields, per-atom heat flux, and thermo-mechanical stress. Key findings include architecture-dependent heat-flow pathways, interfacial thermal resistance, and higher effective conductivity in fin architectures relative to fully encapsulated devices, offering actionable insights for thermally aware transistor design. The approach provides a scalable, predictive pathway to investigate phonon-mediated heat transport and thermomechanical coupling in next-generation electronics, addressing self-heating challenges at the device scale while retaining atomic-level detail.

Abstract

Self-heating in next-generation, high-power-density field-effect transistor limits performance and complicates fabrication. Here, we introduce NEP-FET, a machine-learned framework for device-scale heat transport simulations of field-effect transistors. Built upon the neuroevolution potential, the model extends a subset of the OMat24 dataset through an active-learning workflow to generate a chemically diverse, interface-rich reference set. Coupled with the FETMOD structure generator module, NEP-FET can simulate realistic field-effect transistor geometries at sub-micrometer scales containing millions of atoms, and delivers atomistic predictions of temperature fields, per-atom heat flux, and thermal stress in device structures with high fidelity. This framework enables rapid estimation of device-level metrics, including heat-flux density and effective thermal conductivity. Our results reveal pronounced differences in temperature distribution between fin-type and gate-all-around transistor architectures. The framework closes a key gap in multiscale device modeling by combining near-quantum-mechanical accuracy with device-scale throughput, providing a systematic route to explore heat transport and thermo-mechanical coupling in advanced transistors.

Figures (4)

• Figure 1: Overview of the NEP-FET framework and representative geometries. (a) The NEP-FET framework is used for the simulation of device-level systems. The training set consists mainly of three components: (i) structures from OMat24 omat24, (ii) configurations generated by , and (iii) configurations obtained via . These training sets are then processed and analyzed before being integrated into for training. A realistic all-atom model is then generated using the FETMOD module. Finally, device-level property calculations are performed using -accelerated software. (b) shows two typical structures established using FETMOD module: Fin and , with typical device dimensions marked. Different colored regions are used to group the atomic models to accommodate subsequent -related calculations. (c) A magnified view shows the detailed features of the device structure.
• Figure 2: Dataset composition for NEP-FET and training accuracy. (a) Distribution of the NEP-FET datasets in the reduced descriptor space spanned by the first two principal components. The color intensity indicates the average per-atom energy (in units of eV/atom) in the NEP-FET dataset, while the dot size represents the number of atoms contained in each individual training configuration. b Evolution of the training loss for the NEP-FET model. (c) shows the prediction of the interfacial heat transport properties of SiO$_2$ and HfO$_2$ materials by the NEP-FET model, demonstrating that the model can accurately capture the interfacial heat transport properties of the system chen2017aip. (d) Final force-prediction accuracy of the force prediction ( = 287.5 meV Å$^{-1}$). (e) shows the benchmark results of computational efficiency of NEP-FET and traditional empirical potential model (Tersoff-SiO$_2$Shinji2007CMS) in SiO$_2$ system.
• Figure 3: Thermal-property model of NEP-FET devices. (a, b) Steady-state temperature maps for Fin and , respectively. Heat-source locations are defined in \ref{['fig:framework']}b,d. The sections are taken normal to the two device interfaces; light-blue boxes delineate the regions from which the special cross-sections are extracted. Color encodes local temperature (see color bar). Green solid, red dashed, and blue dotted traces label the source, gate and drain regions, respectively. Position-dependent temperature profiles are plotted for (c) Fin and (d) . (e) Heat-flow distributions in the heat-source and heat-sink regions for both devices.
• Figure 4: Atomic-scale analysis of device properties. (a) Per-atom heat-flux map of the device. Three dotted-line profiles show how the heat flux varies with position across the three regions: the left profile reports the global heat-flux-position relation for the entire device, whereas the upper and lower profiles give the corresponding relations for the grey-shaded subregions in the map. (b) Per-atom von Mises stress Wang1997Mises distribution, with color indicating magnitude (see color bar). (c) Von Mises stress analysis of structures in different cross sections. Positional annotations within the corresponding regions use colors and line styles consistent with the profiles.