HOPPS: Hardware-Aware Optimal Phase Polynomial Synthesis with Blockwise Optimization for Quantum Circuits

TL;DR

This work addresses the challenge of hardware-aware, optimal synthesis for quantum circuits restricted to {CNOT, R_z} gates by introducing HOPPS, a SAT-based framework that can produce CNOT-count or CNOT-depth optimal circuits under device connectivity. It combines a common encoding with specialized constraints to achieve doubly optimal solutions, and further extends to practical circuit optimization via peephole and iterative blockwise strategies. A key contribution is the iterative blockwise optimization that partitions large blocks, enabling parallel SAT solving and scalable convergence toward improved Ct and Dp metrics. Empirical results on IBM devices and QAOA-like benchmarks show substantial reductions in Ct and Dp compared to Qiskit and other baselines, along with favorable runtime characteristics and scalability. These findings support the practicality of HOPPS for integration into end-to-end quantum compilers and for generating hardware-aware optimization templates and datasets.

Abstract

Blocks composed of {CNOT, Rz} are ubiquitous in modern quantum applications, notably in circuits such as QAOA ansatzes and quantum adders. After compilation, many of them exhibit large CNOT counts or depths, which lowers fidelity. Therefore, we introduce HOPPS: a SAT-based hardware-aware optimal phase polynomial synthesis algorithm that could generate {CNOT, Rz} blocks with CNOT count or depth optimality. Sometime {CNOT, Rz} blocks are large, such as in QAOA ansatzes, HOPPS's pursuit of optimality limits its scalability. To address this issue, we introduce an iterative blockwise optimization strategy: large circuits are partitioned into smaller blocks, each block is optimally refined, and the process is repeated for several iterations. Empirical results show that HOPPS is more efficient comparing with existing near optimal synthesis tools. Used as a peephole optimizer, HOPPS reduces the CNOT count by up to 50.0% and the CNOT depth by up to 57.1% under OLSQ. For large QAOA circuit, after mapping by Qiskit, circuit can be reduced CNOT count and depth by up to 44.4% and 42.4% by our iterative blockwise optimization. Index Terms-Phase Polynomial, Quantum Circuit Synthesis, Quantum Circuit Optimization.

Figures (5)

• Figure 1: Explanation of Phase Polynomial Representation and Synthesis. (a) Extracting the phase polynomial representation from a QAOA circuit. The circuit is scanned from beginning to end, starting with an identity matrix. Each CNOT gate updates the circuit’s parity matrix. When an $R_z(\theta)$ gate is encountered, the parity vector associated with that qubit is recorded and stored in the table $T$. After processing the entire circuit, only the final circuit parity matrix $G$ and the table $T$ are retained. (b) Synthesizing a circuit from the phase polynomial representation. CNOT gates are iteratively added, and the parity matrix is updated accordingly. When a qubit’s parity vector matches one in $T$, an $R_z(\theta)$ gate is inserted. After all $t \in T$ are found, we continuously add CNOT gates to make the parity match $G$. Note: This process is not used in this paper; it is provided solely to aid in understanding the problem.(c) Linear hardware topology. The circuits in (a), (b), and (e) obey this constraint, meaning that qubit 1 and qubit 3 cannot be directly connected. (d) Effect of a CNOT gate on circuit parity. A CNOT operation updates the parity matrix by applying a bitwise XOR between the control and target vectors, replacing the control vector with the result. (e) Optimal solution for the QAOA circuit in (a) under the hardware topology in (c).
• Figure 2: Overview of the coupling map (qubit-connectivity topology) for the ibmq_melbourne system and ibmq_kyiv subsystem. Nodes represent physical qubits, and edges indicate allowed two-qubit gate operations on two physical qubits.
• Figure 3: A pipeline overview of the Blockwise Optimization process: we first partition the circuit into blocks and then apply HOPPS in parallel to optimize each block. Afterward, we track metrics such as CNOT count and CNOT depth to check for convergence. If the circuit has converged, it is compiled for execution on a real device; otherwise, the process is repeated.
• Figure 4: Behavior of Iterative Blockwise Optimization Strategy.
• Figure 5: HOPPS vs. QSearch davis2020towards Synthesis Time. Under equivalent synthesis quality—defined as achieving the same CNOT count and depth—HOPPS requires less execution time compared to QSearch. In the left figure, we fix the number of qubits and vary the number of edges to examine how synthesis time scales with circuit depth. In the right figure, we maintain a similar number of edges while increasing the number of qubits to evaluate scalability with circuit width. The results show that HOPPS is more scalable, particularly depth HOPPS. This demonstrates the advantage of HOPPS for synthesizing $\{ \text{CNOT}, R_z(\theta) \}$ circuits.