Rapid fabrication of clean van der Waals nanochannels using Mask and Stack method

TL;DR

The paper addresses the contamination and long fabrication timelines that hinder 2D van der Waals nanochannels by introducing the Mask & Stack method, a stencil-based, resist-free fabrication approach that yields ultraclean nanochannels via dry transfer. It demonstrates rapid manufacturing with polymer-free interfaces, validated by AFM and Raman analyses that show minimal residues and pristine interlayer contacts. Ionic transport experiments through monolayer MoS$_2$ channels reveal surface-governed conductance and steric exclusion consistent with extreme confinement, along with strong device reproducibility and stability over days. The method is compatible with diverse 2D materials and scalable toward high-throughput production, offering a pathway for automated manufacturing of nanofluidic, electronic, and photonic heterostructures with enhanced cleanliness and reliability.

Abstract

Two-dimensional (2D) nanochannels have emerged as a pivotal platform for exploring nanoscale hydrodynamics and electrokinetics. Conventional fabrication methods to make nanochannels often introduce polymer contamination and require lengthy processing, limiting device performance and scalability. Here we introduce the Mask & Stack method, employing silicon nitride stencil mask combined with dry transfer stacking to rapidly fabricate ultraclean vdW nanochannels within hours. This polymer-free approach preserves pristine interfaces, confirmed by atomic force microscopy and Raman spectroscopy, and yields nanochannel devices exhibiting reproducible ionic transport and long-term stability. The streamlined process is compatible with diverse 2D materials and promising for upscale production. Our method advances the fabrication of nanofluidic and 2D heterostructure devices, facilitating applications in quantum transport, photonics, energy harvesting, and sensing technologies requiring high-throughput, contamination-free heterostructure architectures.

Figures (14)

• Figure 1: Fabrication of vdW nanochannel devices using SiN stencil mask.a, Schematic illustration of the device fabrication workflow. Wafer-scale SiN mask production creating stencil masks with designated patterns, following standard lithography and etching processes. (Step 1) using pre-patterned SiN as etching mask, spacer layer is made through RIE etching from backside. (Step 2) the spacer layer is picked up by PDMS stamp using dry transfer method, with exfoliated top crystal on the stamp. (Step 3) a bottom crystal is then picked up to complete the sandwich stacking. (Step 4) the encapsulated nanochannel is aligned and released onto a SiN membrane with predefined slit opening. b, Schematic of the final vdW nanochannel device, the red arrow indicates the mass transport pathway through the nanochannels. c, Optical images from each fabrication step corresponding to the schematics shown in steps 1-4. Dashed lines show the contours of the named layers on each image. Scale bars, 20 $\mu$m.
• Figure 2: Cleanliness of the nanochannels characterized by AFM.a–e. AFM images of MoS$_2$ spacers with varying thicknesses: a, 1L, b, 2L, c, 3L, d, 4L, and e, 5L. These spacers are imaged on top of another 2D crystal and PDMS stamp. All spacers exhibit well-defined edges and clean surface. The dashed white line in a indicates the positions where the height profiles of these channels are taken. The red box in e shows the area where the roughness in g is obtained. f, Histogram representation of surface roughness for the boxed region in e, showing RMS roughness of $\sim$16 pm. g, Height profiles across one of the slits in each AFM images in a-e, showing step height consistent with the reported interlayer spacing of MoS$_2$. h, AFM image of a FLG spacer on graphite bottom crystal on PDMS stamp. i, AFM topography of the FLG channel surface after assembly, showing visible sagging of the top layer above the channels. j, AFM topography of the same channels after filling with water, showing channels leveling up with the nearby spacers. k, Height profiles across spacers and channels as indicated by the white dashed line in h and black dashed lines in i and j. Scale bars on all images: 1 $\mu$m.
• Figure 3: Raman mapping of nanochannels. a, Schematic illustration of the device cross-section, consisting of MLG encapsulated between the hBN spacer and top layer. b, Raman mapping of the FWHM of MLG 2D band $\Gamma_\mathrm{2D}$. The dashed blue line contours the MLG region. c, Second-derivative maps for the G (top) and 2D (bottom) peaks along the dashed white line in b. The horizontal dashed lines are visual guides for average peak positions. The two vertical solid lines mark representative positions for spacer and channel regions, respectively, used in d and e. d-e, Lorentzian fits to the G peak (d) and 2D peak (e) for the spacer area (red) and channel area (blue).
• Figure 4: Ionic transport through monolayer MoS$_2$ nanochannel. a, Schematic illustration of the ionic transport measurement setup. b, Conductance for the nanochannel device with 1L MoS$_2$ as the spacer. c, Conductivity of various salt solutions (0.1 M) through nanochannels. Blue open squares denote bulk conductivity of the corresponding salts. d, Effective ion mobility inside the nanochannel (squares) compared to bulk values (diamonds) from literaturenightingale1959phenomenologicalhaynes2016crc. e, Ionic conductivity of 4L MoS$_2$ nanochannels as a function of channel number (N). Insets: schematics of devices containing 2, 5, and 13 parallel channels. f, Comparison between Mask $\&$ Stack method (yellow) and conventional lithography-based methods (gray).
• Figure S1: Fabrication and characterization of the SiN stencil.a, Schematic illustration of the fabrication process. A SiN/Si/SiN wafer was processed by photolithography and RIE to define the a large SiN window (step 1). The exposed Si is then selectively removed by KOH etching (step 2) to form a freestanding SiN membrane. EBL and RIE are then used to pattern parallel lines into the freestanding SiN membrane (step 3), yielding the final SiN stencil for nanochannels. b, Photograph of a 4-inch SiN/Si/SiN wafer patterned with 69 SiN stencil masks, demonstrating wafer-scale production and reproducibility of the process. Wafer-scale production enables its upscale using automated assembly workflows and potential integration with CMOS architectures. c, Optical image of a SiN stencil with patterned nanochannels. d, SEM images of SiN stencil. Inset: zoom in version of the channel area. Scale bar: 30µm in c, 10µm in d, and 2µm in the inset of d.