Passive mechanical logic via topology-optimized acoustic waveguides

TL;DR

This work addresses the demand for low-power computation by encoding logic in wave propagation within a passive elastic medium. It introduces a topology-optimization framework to design void-engineered waveguides that steer vibroacoustic waves to readouts corresponding to logical outputs, enabling gates and a full adder without active actuation. Key contributions include a unified gate-design method, numerical demonstrations of AND, XOR, and OR logic, experimental validation of gates at around 92 kHz, and a mechanically integrated full adder circuit. The approach offers fast, perturbation-robust, low-power mechanical computation and scalable pathways to more complex passive signal processing devices.

Abstract

Growing energy demands of modern digital devices necessitate alternative, low-power computing mechanisms. When incident loads take the form of acoustic or vibrational waves, the ability to mechanically process information eliminates the need for transduction, paving the way for passive computing. Recent studies have proposed systems that learn and execute mechanical logic through buckling, bistability, and origami-inspired lattices. However, owing to the large timescales of shape morphing, such concepts suffer from slow operation or require active stimulation of adaptive materials. To address these limitations, we present a novel approach to mechanical logic, leveraging the rich dynamics of wave propagation in elastic structures. In lieu of traditional forward-design tools, such as band diagrams and transmission spectra, we employ a multi-faceted topology optimization approach, enabling us to identify candidate waveguide configurations within an extremely large design space. By incorporating voids within an otherwise uniform substrate, the optimized waveguides are able to precisely manipulate wave propagation paths, triggering desirable interferences of the scattered wavefield that culminate in energy localization at readouts corresponding to a given logic function. An experimental setup is used to demonstrate the efficacy of such logic gates and their resilience to non-uniform loading. By implementing these building blocks into a mechanical adder, we demonstrate the scalable deployment of more sophisticated mechanical computing circuits, opening up new avenues in mechanical signal processing and physical computing.

Figures (9)

• Figure 1: Forward versus inverse design frameworks for mechanical wave-based computing. In a forward design approach, physics-driven tools such as dispersion diagrams and transmission spectra, among others, are used to realize candidate configurations which are typically ordered in shape and geometry and rely on human intuition. In contrast, an inverse design approach utilizes algorithmic (such as topology optimization) or data-driven tools to determine an optimal structure starting from a desired outcome, exploring a large design space in the process. This path typically produces non-ordered structures which, while effective in satisfying quantifiable objectives, are not necessarily intuitive.
• Figure 2: Flowchart representation of the topology optimization algorithm and the associated filtering procedure of a wave-based mechanical logic gate. The optimization framework begins by initializing the design variable $\theta_c$, followed by filtering and wavefield generation. The optimizer maximizes the objective function, $\bar{w}_{\mathrm{a}}$, subject to the constraint $\bar{w}_{\mathrm{a}} / \bar{w}_{\mathrm{ia}} > r$. The waveguide design is updated iteratively until convergence is achieved. The central schematic shows an optimal design resulting from this process. The filtering procedure inset details the post-processing of the material density field to enforce a binary material distribution for fabrication purposes.
• Figure 3: (a) Uniform gate configuration (pre-optimization), showing all input and output legs, the optimization domain, and incident wave locations. Output regions where the averaged out-of-plane displacements, $\bar{w}_{\mathrm{a,ia}}$, are evaluated in each iteration of the optimization process are marked by black dashed boxes. (b) Schematic diagram outlining the process of obtaining a unified gate design per logic operation through an example AND gate. For better visualization, the displayed mesh comprises larger elements than those used in the simulations. The truth table of the AND gate is shown on the left for all four possible input scenarios, $i$. Excitation forces at the input ports $A$ and $B$ are marked by ${F}_{A,i}$ and ${F}_{B,i}$, respectively. All active (1) legs are highlighted in green, active (0) legs are highlighted in red, and inactive legs are left gray. The optimizer maximizes the aggregate average displacement of the active legs across all four input scenarios, $\Sigma_{i=1}^4 \bar{w}_{\mathrm{a},i}$, with four constraints concurrently imposed ensuring that the ratio of active-to-inactive output displacements exceeds the preset threshold in each of the four cases separately, i.e., $[\bar{w}_{\mathrm{a},i}/\bar{w}_{\mathrm{ia},i}] > 1.5$. To guarantee a unified waveguide design for all $i$ values, the optimized geometry from the ($i=1$) case is replicated across the remaining three cases for each iteration. The evolution of the objective function for select $\beta$ values is illustrated in the top plot on the far right side, whereas the variation of the four concurrent constraints throughout the iterative process for $\beta=256$ step is shown on the bottom plot. While the optimizer is set to run up to $150$ iterations for each $\beta$ step, a step concludes earlier if convergence is reached, i.e., when changes in the objective fall within a tolerance of $10^{-6}$, as captured by the two plots.
• Figure 4: Performance of the optimized wave-based mechanical logic gates. The top panel displays the finalized optimized gate designs for AND (left) and XOR (right) gates, whose binary output material index, $\theta_b$, indicates the fraction of solid material remaining after spatial placement of voids within the optimization domain. The lower panels show the displacement wavefields for both gates across all four cases of the truth table, i.e., $i=1$ through $4$. The bar graphs adjacent to the output legs of each wavefield represent the average displacement magnitudes in the active, $\bar{w}_{\mathrm{a},i}$, and inactive, $\bar{w}_{\mathrm{a},ia}$, legs, with green bars denoting (1) outputs, red bars denoting (0) outputs, and gray bars denoting inactive legs.
• Figure 5: Time evolution of the wave-based AND gate subject to two sets of inputs, $i=1$ and $4$. Wavefields are shown for both cases at five snapshots, $t_0$, $t_1$, $t_2$, $t_3$, and $t_4$, where $t_0$ is shortly after input excitations are applied and $t_4$ shows the gate's response as the correct readout manifests itself in the output legs. Significant milestones are indicated using the dashed boxes. The time domain analysis demonstrates the progression of the gate's performance in both cases, and captures the emergence of reflected waves over time, which backfill some of the inactive input legs. The eventual wavefields show close agreement with the steady state (frequency domain) results of Fig. \ref{['Fig4']}, and confirm the negligible effect of backpropagation on the gate's outputs across all input scenarios.