Table of Contents
Fetching ...

GANGR: GAN-Assisted Scalable and Efficient Global Routing Parallelization

Hadi Khodaei Jooshin, Inna Partin-Vaisband

TL;DR

GANGR tackles the scalability bottlenecks of global routing by replacing heuristic net batching with a Wasserstein GAN–assisted, layer-aware batching framework. The method learns complex net-interference patterns to form fewer, larger batches, enabling GPU-accelerated parallel routing while preserving routing quality. Key innovations include 3D layer-aware overlap detection, memory-efficient batch validation, and an end-to-end WGAN training regime with gradient penalty. Experiments on ISPD'24 benchmarks show up to 40% faster runtimes with negligible degradation in wirelength, via count, and congestion metrics, indicating strong practical impact for large-scale IC designs.

Abstract

Global routing is a critical stage in electronic design automation (EDA) that enables early estimation and optimization of the routability of modern integrated circuits with respect to congestion, power dissipation, and design complexity. Batching is a primary concern in top-performing global routers, grouping nets into manageable sets to enable parallel processing and efficient resource usage. This process improves memory usage, scalable parallelization on modern hardware, and routing congestion by controlling net interactions within each batch. However, conventional batching methods typically depend on heuristics that are computationally expensive and can lead to suboptimal results (oversized batches with conflicting nets, excessive batch counts degrading parallelization, and longer batch generation times), ultimately limiting scalability and efficiency. To address these limitations, a novel batching algorithm enhanced with Wasserstein generative adversarial networks (WGANs) is introduced in this paper, enabling more effective parallelization by generating fewer higher-quality batches in less time. The proposed algorithm is tested on the latest ISPD'24 contest benchmarks, demonstrating up to 40% runtime reduction with only 0.002% degradation in routing quality as compared to state-of-the-art router.

GANGR: GAN-Assisted Scalable and Efficient Global Routing Parallelization

TL;DR

GANGR tackles the scalability bottlenecks of global routing by replacing heuristic net batching with a Wasserstein GAN–assisted, layer-aware batching framework. The method learns complex net-interference patterns to form fewer, larger batches, enabling GPU-accelerated parallel routing while preserving routing quality. Key innovations include 3D layer-aware overlap detection, memory-efficient batch validation, and an end-to-end WGAN training regime with gradient penalty. Experiments on ISPD'24 benchmarks show up to 40% faster runtimes with negligible degradation in wirelength, via count, and congestion metrics, indicating strong practical impact for large-scale IC designs.

Abstract

Global routing is a critical stage in electronic design automation (EDA) that enables early estimation and optimization of the routability of modern integrated circuits with respect to congestion, power dissipation, and design complexity. Batching is a primary concern in top-performing global routers, grouping nets into manageable sets to enable parallel processing and efficient resource usage. This process improves memory usage, scalable parallelization on modern hardware, and routing congestion by controlling net interactions within each batch. However, conventional batching methods typically depend on heuristics that are computationally expensive and can lead to suboptimal results (oversized batches with conflicting nets, excessive batch counts degrading parallelization, and longer batch generation times), ultimately limiting scalability and efficiency. To address these limitations, a novel batching algorithm enhanced with Wasserstein generative adversarial networks (WGANs) is introduced in this paper, enabling more effective parallelization by generating fewer higher-quality batches in less time. The proposed algorithm is tested on the latest ISPD'24 contest benchmarks, demonstrating up to 40% runtime reduction with only 0.002% degradation in routing quality as compared to state-of-the-art router.

Paper Structure

This paper contains 18 sections, 1 equation, 1 figure, 4 tables, 3 algorithms.

Figures (1)

  • Figure 1: Net overlap analysis with conflicts (excluded from parallel routing) shown as hatched regions, (a) the bounding box method flags large overlap, limiting parallelism (used by many algorithms, e.g., CUGR2 liu2020CUGRDeatailRouting, (b) the layer-agnostic analysis in InstantGRlin2024instantgr1, which conservatively marks vertical and horizontal conflicts across all layers, underutilizing available parallelism, and (c) the proposed layer-aware method considers overlaps only within the same metal layer, avoiding false conflicts between nets on different layers, as illustrated by the black and blue nets in the 3D view.