Uncertainty Removal in Verification of Nonlinear Systems against Signal Temporal Logic via Incremental Reachability Analysis
Antoine Besset, Joris Tillet, Julien Alexandre dit Sandretto
TL;DR
The paper tackles uncertainty in verifying STL properties for nonlinear continuous-time systems by integrating reachability analysis with Boolean interval arithmetic. It introduces a unitary-signal framework and a marker-based uncertainty tracking mechanism that distinguishes whether indeterminacy arises from over-approximation or incomplete simulations, enabling selective refinement of only the relevant reachable sets. The approach supports both offline and online monitoring and contracts/refines the reachable tube adaptively to improve precision while avoiding unnecessary recomputation. A nonlinear oscillator case study demonstrates substantial reductions in satisfaction ambiguity and favorable computational performance compared with baseline methods.
Abstract
A framework is presented for the verification of Signal Temporal Logic (STL) specifications over continuous-time nonlinear systems under uncertainty. Based on reachability analysis, the proposed method addresses indeterminate satisfaction caused by over-approximated reachable sets or incomplete simulations. STL semantics is extended via Boolean interval arithmetic, enabling the decomposition of satisfaction signals into unitary components with traceable uncertainty markers. These are propagated through the satisfaction tree, supporting precise identification even in nested formulas. To improve efficiency, only the reachable sets contributing to uncertainty are refined, identified through the associated markers. The framework allows online or offline monitoring to adapt to incremental system evolution while avoiding unnecessary recomputation. A case study on a nonlinear oscillator demonstrates a significant reduction in satisfaction ambiguity, highlighting the effectiveness of the approach.
