Gate-level boolean evolutionary geometric attention neural networks

TL;DR

The paper addresses the need for interpretable, hardware-efficient AI for spatial data by modeling images as Boolean fields on 2D manifolds and evolving them with trainable reaction-diffusion logic kernels. It introduces a gate-level Boolean evolution framework that integrates a Boolean self-attention mechanism based on XNOR similarity and a Boolean Rotary Position Encoding to form a Transformer-like architecture operating entirely in the Boolean domain, with differentiable training via continuous relaxations. The key contributions include the first gate-level Boolean geometric attention network, analysis of expressive power and hardware efficiency, and demonstrations of applicability to high-speed image processing, interpretable AI, and hardware acceleration. Significance lies in enabling transparent, verifiable AI with potential for ultra-low-power, parallel hardware implementations, while offering a bridge between symbolic logic and perception tasks for future AI systems.

Abstract

This paper presents a gate-level Boolean evolutionary geometric attention neural network that models images as Boolean fields governed by logic gates. Each pixel is a Boolean variable (0 or 1) embedded on a two-dimensional geometric manifold (for example, a discrete toroidal lattice), which defines adjacency and information propagation among pixels. The network updates image states through a Boolean reaction-diffusion mechanism: pixels receive Boolean diffusion from neighboring pixels (diffusion process) and perform local logic updates via trainable gate-level logic kernels (reaction process), forming a reaction-diffusion logic network. A Boolean self-attention mechanism is introduced, using XNOR-based Boolean Query-Key (Q-K) attention to modulate neighborhood diffusion pathways and realize logic attention. We also propose Boolean Rotary Position Embedding (RoPE), which encodes relative distances by parity-bit flipping to simulate Boolean ``phase'' offsets. The overall structure resembles a Transformer but operates entirely in the Boolean domain. Trainable parameters include Q-K pattern bits and gate-level kernel configurations. Because outputs are discrete, continuous relaxation methods (such as sigmoid approximation or soft-logic operators) ensure differentiable training. Theoretical analysis shows that the network achieves universal expressivity, interpretability, and hardware efficiency, capable of reproducing convolutional and attention mechanisms. Applications include high-speed image processing, interpretable artificial intelligence, and digital hardware acceleration, offering promising future research directions.