ATMPlace: Analytical Thermo-Mechanical-Aware Placement Framework for 2.5D-IC

TL;DR

ATMPlace is presented, the first analytical placer for 2.5D ICs that jointly optimizes wirelength, peak temperature, and operational warpage using physics-based compact models and generates Pareto optimal placements for systems with dozens of chiplets.

Abstract

Rising demand in AI and automotive applications is accelerating 2.5D IC adoption, with multiple chiplets tightly placed to enable high-speed interconnects and heterogeneous integration. As chiplet counts grow, traditional placement tools, limited by poor scalability and reliance on slow simulations, must evolve beyond wirelength minimization to address thermal and mechanical reliability, critical challenges in heterogeneous integration. In this paper, we present ATMPlace, the first analytical placer for 2.5D ICs that jointly optimizes wirelength, peak temperature, and operational warpage using physics-based compact models. It generates Pareto optimal placements for systems with dozens of chiplets. Experimental results demonstrate superior performance: 146 percent and 52 percent geometric mean wirelength improvement over TAP 2.5D and TACPlace, respectively, with 3 to 13 percent lower temperature and 5 to 27 percent less warpage, all achieved approximately 10 times faster. The proposed framework is general and can be extended to enable fast, scalable, and reliable design exploration for next-generation 2.5D systems.

Figures (8)

• Figure 1: Layered cross-section (left) and isometric illustration of thermal deformation (right) in 2.5D-IC structure.
• Figure 2: Illustration of the ATMPlace framework, including the compact model fitting and placement flow.
• Figure 3: Illustration of the D2D link between chiplets (left), and a portion of the detailed package bump map of a $\times16$ module (right). The seashell and green circles are the I/O supply (Vccio) and ground reference (Vss) bump, while the blue circles represent the $Tx/Rx$ bumps, respectively.
• Figure 4: Thermo-mechanical field comparison for a placement in Case 1: (a) ground truth, (b) compact model prediction.
• Figure 5: Placement layouts for Case 3. Upper row: wirelength-driven optimization. Lower row: thermo-mechanical-aware optimization. CPU and DRAM dimensions: $9 \times 8~\mathrm{mm}^2$ and $9 \times 9~\mathrm{mm}^2$, respectively.