Power Flow Solution in Unbalanced 3-Wire MV and 4-Wire LV Networks Using Symmetrical and Eigen-basis Coordinates
Abduljalil S. Aljadani, Firdous U. Nazir, Bikash C. Pal, Izudin Džafić, Rabih A. Jabr
TL;DR
This paper tackles the challenge of efficient, accurate power-flow calculations for integrated MV and four-wire LV distribution networks under unbalanced conditions, where traditional symmetric-coordinate methods fall short. It introduces an eigen-basis modelling framework that diagonalizes the LV line admittance via eigenvector decomposition, transforming the bus admittance matrix to a mixed symmetrical/eigen-basis form and enabling parallelized solution of decoupled sub-networks. Key contributions include the diagonalization of four-wire LV feeders, sensitivity analysis of Carson’s equations, the decomposed YBUS approach, and demonstrated memory and time savings, with substantial speed-ups in Volt/Var Control workflows. The proposed method significantly reduces LU fill-ins and computation time (up to 3.63× on large networks) and lowers memory requirements by more than 50%, making it well-suited for real-time operation and AI-assisted VVC training.
Abstract
The large penetration of distributed generations impacts both the secondary low-voltage (LV) and the primary medium-voltage (MV) segments of the distribution network. Optimizing power flow calculations for the integrated MV/LV networks is crucial for the real-time management of modern distribution networks. Traditional methods in symmetrical coordinates are primarily limited to the three-wire model of three-phase networks, often leading to inaccuracies in power flow calculations when applied to three-phase four-wire LV segments. This paper introduces a novel power flow method for integrated three-wire MV and four-wire LV networks. Using eigenvector decomposition to diagonalize the admittance matrix of four-wire LV lines, the proposed method improves the computational efficiency of power flow calculations and accurately calculates the neutral-to-ground voltage. The results of the case studies show over 50\% reduction in the number of non-zero elements in the LU factors of the bus admittance matrix, and speed-up factors of 2.78 on the IEEE 123-node test system and 3.63 on the IEEE 8500-node test system in execution times for Volt/Var control (VVC), compared to the phase coordinates model.
