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Interfacial and bulk switching MoS2 memristors for an all-2D reservoir computing framework

Asmita S. Thool, Sourodeep Roy, Prahalad Kanti Barman, Kartick Biswas, Pavan Nukala, Abhishek Misra, Saptarshi Das, and Bhaswar Chakrabarti

TL;DR

The study presents a fully memristive reservoir computing framework implemented on a single 2D MoS2 platform that combines volatile short-term memory in monolayer MoS2 reservoirs with nonvolatile analog readout in multilayer MoS2 synapses. Through CVD growth, HRSTEM analysis, and crossbar fabrication, the authors demonstrate robust, nonfilamentary bulk switching, high uniformity, and reliable analog conductance tuning. The integrated system achieves 89.56% accuracy in spoken-digit recognition and can solve nonlinear time-series problems, highlighting the potential for energy-efficient, scalable neuromorphic hardware based on two-dimensional materials. These results establish a practical pathway for all-2D reservoir computing with demonstrated performance and inform design considerations for membraneless, bulk-dominated memristors in neuromorphic architectures.

Abstract

In this study, we design a reservoir computing (RC) network by exploiting short- and long-term memory dynamics in Au/Ti/MoS$_2$/Au memristive devices. The temporal dynamics is engineered by controlling the thickness of the Chemical Vapor Deposited (CVD) MoS$_2$ films. Devices with a monolayer (1L)-MoS$_2$ film exhibit volatile (short-term memory) switching dynamics. We also report non-volatile resistance switching with excellent uniformity and analog behavior in conductance tuning for the multilayer (ML) MoS$_2$ memristive devices. We correlate this performance with trap-assisted space-charge limited conduction (SCLC) mechanism, leading to a bulk-limited resistance switching behavior. Four-bit reservoir states are generated using volatile memristors. The readout layer is implemented with an array of nonvolatile synapses. This small RC network achieves 89.56\% precision in a spoken-digit recognition task and is also used to analyze a nonlinear time series equation.

Interfacial and bulk switching MoS2 memristors for an all-2D reservoir computing framework

TL;DR

The study presents a fully memristive reservoir computing framework implemented on a single 2D MoS2 platform that combines volatile short-term memory in monolayer MoS2 reservoirs with nonvolatile analog readout in multilayer MoS2 synapses. Through CVD growth, HRSTEM analysis, and crossbar fabrication, the authors demonstrate robust, nonfilamentary bulk switching, high uniformity, and reliable analog conductance tuning. The integrated system achieves 89.56% accuracy in spoken-digit recognition and can solve nonlinear time-series problems, highlighting the potential for energy-efficient, scalable neuromorphic hardware based on two-dimensional materials. These results establish a practical pathway for all-2D reservoir computing with demonstrated performance and inform design considerations for membraneless, bulk-dominated memristors in neuromorphic architectures.

Abstract

In this study, we design a reservoir computing (RC) network by exploiting short- and long-term memory dynamics in Au/Ti/MoS/Au memristive devices. The temporal dynamics is engineered by controlling the thickness of the Chemical Vapor Deposited (CVD) MoS films. Devices with a monolayer (1L)-MoS film exhibit volatile (short-term memory) switching dynamics. We also report non-volatile resistance switching with excellent uniformity and analog behavior in conductance tuning for the multilayer (ML) MoS memristive devices. We correlate this performance with trap-assisted space-charge limited conduction (SCLC) mechanism, leading to a bulk-limited resistance switching behavior. Four-bit reservoir states are generated using volatile memristors. The readout layer is implemented with an array of nonvolatile synapses. This small RC network achieves 89.56\% precision in a spoken-digit recognition task and is also used to analyze a nonlinear time series equation.

Paper Structure

This paper contains 14 sections, 1 equation, 7 figures.

Figures (7)

  • Figure 1: (a,f) Optical image of CVD grown large area continuous film 1L and multilayer MoS$_2$, respectively, (b-c,g-h) AFM image and corresponding height profile of the continuous MoS$_2$ film showing monolayer and multilayer thickness, (d,i) Raman spectroscopy taken on grown MoS$_2$ verifying the growth of 1L and multilayer MoS$_2$, (e,j) Photoluminance spectroscopy taken on grown MoS$_2$ verifying the growth of 1L and multilayer MoS$_2$ (k,l) PL and (m,n) Raman intensity mapping performed on as grown 1L-MoS$_2$ and multilayer MoS$_2$ on the source substrate SiO$_2$/Si.
  • Figure 2: (a) Schematic image of Au/Ti/1L-MoS$_2$/Au device and, its corresponding (b) Optical image of a 5 $\mu$m $\times$ 5 $\mu$m 1L-MoS$_2$ device, (c) Schematic image of Au/Ti/ML-MoS$_2$/Au device and, its corresponding (d) Optical image of a 5 $\mu$m $\times$ 5 $\mu$m ML-MoS$_2$ device, (e-g) HRSTEM image of a 1L MoS$_2$ device, (h-k) HRSTEM images of a ML-MoS$_2$ device, (l) Interlayer periodicity of ML-MoS$_2$ in the fabricated device.
  • Figure 3: (a) HRSTEM image of a pristine device with the Au/Ti/ML-MoS$_2$/Au stack(from top to bottom). (b) An HRSTEM image of a switched device in the LRS condition showing a conductive path or "filament". (c-d) Defects and Au intercalates in MoS$_2$, away from the filament region. (e) Comparison of atomic fractions of Mo and S in the pristine and switched device shows reduction of S content after switching. (f) Current-voltage characteristics in the HRS and LRS fitted with SCLC transport equation.
  • Figure 4: Characteristics of 16$\times$16 ML-MoS$_2$ crossbar array. All the devices in the array have an area of 7 $\mu$m $\times$ 7 $\mu$m. (a) An SEM image of the developed array, (b) Pulse programming scheme for potentiation (P) and depression (D) operations. One complete P/D cycle starts with potentiation using 45 identical positive pulses followed by depression with 45 identical negative pulses. (c) Multiple P/D cycles performed on one device in the array. (d) P/D operation performed on different devices in the array. (e) Measured endurance up to 10,000 cycles. (f) P/D operation performed over more than 5000 pulses on a device, demonstrating long-term stability of conductance modulation. (g) Cumulative probability of device conductance at 25$^{th}$ pulse in each potentiation cycle.
  • Figure 5: (a) The input pulse stream to create [ 1111 ] state. (b) 16 output states for the input pulse stream varying from [ 0000 ] to [ 1111 ]. Response of a device repeated for same signal recorded 16 times for pulse streams (c) [0010], (d) [0101], (e) [0110], (f) [1010], (Device area 7 $\mu$m $\times$ 7 $\mu$m).
  • ...and 2 more figures