CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference

TL;DR

This paper addresses the frequent functional errors in HDL designs produced by LLMs due to hallucinations. It proposes CorrectHDL, an agentic HDL design framework that uses HLS-generated HDL as a bit-accurate functional reference to steer LLM-based HDL generation. Key methods include function-level C/C++ decomposition to preserve hardware semantics, RAG-assisted syntax repair, and a differential verification loop with HLS references, augmented by boundary instrumentation and backward slicing for integration. Across 12 tasks, CorrectHDL delivers substantial gains in synthesis correctness and PPA, achieving about 15.49% syntax pass-rate improvement, 28.05% functional improvement, 38.54% top-level gain, and 24.83% area and 26.98% power reductions compared with conventional HLS, approaching human-engineered quality.

Abstract

Large Language Models (LLMs) have demonstrated remarkable potential in hardware front-end design using hardware description languages (HDLs). However, their inherent tendency toward hallucination often introduces functional errors into the generated HDL designs. To address this issue, we propose the framework CorrectHDL that leverages high-level synthesis (HLS) results as functional references to correct potential errors in LLM-generated HDL designs.The input to the proposed framework is a C/C++ program that specifies the target circuit's functionality. The program is provided to an LLM to directly generate an HDL design, whose syntax errors are repaired using a Retrieval-Augmented Generation (RAG) mechanism. The functional correctness of the LLM-generated circuit is iteratively improved by comparing its simulated behavior with an HLS reference design produced by conventional HLS tools, which ensures the functional correctness of the result but can lead to suboptimal area and power efficiency. Experimental results demonstrate that circuits generated by the proposed framework achieve significantly better area and power efficiency than conventional HLS designs and approach the quality of human-engineered circuits. Meanwhile, the correctness of the resulting HDL implementation is maintained, highlighting the effectiveness and potential of agentic HDL design leveraging the generative capabilities of LLMs and the rigor of traditional correctness-driven IC design flows.

Figures (15)

• Figure 1: Traditional manual HDL design flow.
• Figure 2: (a) LLM-aided HDL design flow; (b) High-Level Synthesis (HLS) flow; (c) Our proposed concept.
• Figure 3: Examples of HDL Generation via LLM and HLS.
• Figure 4: Proposed HDL design agent.
• Figure 5: LLM-assisted HDL generation.