Medusa: Detecting and Removing Failures for Scalable Quantum Computing

TL;DR

Medusa addresses scalable quantum error correction by automating flag-based fault tolerance during circuit compilation. It introduces a failure-rate framework based on stabilizer comparisons between noisy and noiseless ICM circuits and a scalable heuristic to insert unique weight flags, plus a method to upper-bound FR with perfect flags and to tune flag reliability via an error multiplier $m$ using binary search. The approach is evaluated on adder-like circuits, showing that a small number of well-placed, partially protected flags can make large circuits perform like smaller ones, and that flag placement and fault-tolerance tuning influence resource requirements. By mapping the required flag reliability to surface-code distances and qubit counts, Medusa provides practical hardware estimates and highlights a cost-effective alternative to fully fault-tolerant syndrome extraction. The work lays groundwork for adapting to zoned architectures and extending to multi-flag gadgets.

Abstract

Quantum circuits will experience failures that lead to computational errors. We introduce Medusa, an automated compilation method for lowering a circuit's failure rate. Medusa uses flags to predict the absence of high-weight errors. Our method can numerically upper bound the failure rate of a circuit in the presence of flags, and fine tune the fault-tolerance of the flags in order to reach this bound. We assume the flags can have an increased fault-tolerance as a result of applying surface QECs to the gates interacting with them. We use circuit level depolarizing noise to evaluate the effectiveness of these flags in revealing the absence of the high-weight stabilizers. Medusa reduces the cost of quantum-error-correction (QEC) because the underlying circuit has a lower failure rate. We benchmark our approach using structured quantum circuits representative of ripple-carry adders. In particular, our flag scheme demonstrates that for adder-like circuits, the failure rate of large-scale implementations can be lowered to fit the failure rates of smaller-scale circuits. We show numerically that a slight improvement in the local fault-tolerance of the flag-qubits can lead to a reduction in the overall failure rate of the entire quantum circuit.

Figures (5)

• Figure 1: Quantum circuits: (a) Medusa is based on ICM circuits paler2017faultvijayan2024compilation, e.g. gate teleportation, which consist entirely of CNOT gates, initializations and measurements; (b) A bit flip error occurring in location X in the original circuit is caught by the flag: the measurement of the flag would give 1 instead of 0 as the error is propagated to the flag through the blue CNOT gate. At the end of the circuit the error is present on the first, second and last qubit. By post-selecting based on the flag measurements and checking the stabilizers of the original ICM circuit we can examine wether or not the flags have successfully caught the errors.
• Figure 2: Flag circuits obtained after adding a flag qubit and gates, marked blue: (a) an X-flag; (b) a Z-flag.
• Figure 3: Medusa for zoned architectures. Illustration for a hypothetical 4 qubit circuit (black circles): (a) The qubits are stored in the storage zone; (b) in order to add two flags to the circuit, two of the qubits are moved to a green encoding zone and are encoded into cat states (dark green), and the resulting encoded state is performing the first CNOT with a fault-tolerant flag (dark blue rectangle) residing in flag zone (previously light blue); (c) after unencoding the physical qubits, these are moved to a CNOT zone where they are executing the ICM circuit; (d) the flagged qubits are moved back to the entangling zones to perform the second CNOT necessary for connecting the flag; (e) finally, the qubits and the flags are moved to the measurement zone.
• Figure 4: Benchmarking results for using $5 \log_{2}(N)$ flags, where N is the size of the adder-like circuit. The horizontal axis is the noise channel strength i.e. the error rate at each gate. (a) The failure rate after post selection the flags; (b) The acceptance rate i.e. what percentage of runs is accepted during post selection using the flags; (c) The difference in failure rate, i.e. the difference between the failure rate of the flagless ICM adder and the flag adder of the same size. (d) Error multiplier m needed to reach $N-1$ target failure rate for different base error rates $p_{ncs}$ (colors). (e) Surface code distance needed to achieve the error rate of the horizontal axis for different $p_{ncs}$ (f) Number of qubits required (incl. surface code) to achieve the failure rate of a size $N-1$ circuit using a circuit of size N considering the $p_{ncs}$ from the colored lines. e.g. circuit size $N=35$ needs around 2500 qubits to get to the FR of $N-1=34$ when considering that the $p_{ncs}$ is 0.001 (yellow).
• Figure 5: Improving a circuit's total failure rate (horizontal axis) by lowering only the flags' failure rate. The error multiplier (color coded) is the factor by which the error rate of the gates attached to the flag qubits is multiplied by. The vertical axis is the size of the adder. Results for perfect flags are red.