TRAM: A Transverse Relaxation Time-Aware Qubit Mapping Algorithm for NISQ Devices

TL;DR

The paper tackles the mismatch between static qubit-mapping strategies and the time-evolving noise in NISQ devices by introducing TRAM, a coherence-aware qubit-mapping framework. TRAM combines three components—CQTP for calibration-informed, noise-aware partitioning; THIM for time-weighted, noise-aware initial mapping; and T-SWAP for time-adaptive SWAP scheduling—to minimize cumulative decoherence. Empirical results on Qiskit-based simulators with realistic noise show TRAM delivering consistent fidelity gains and reductions in gate counts and circuit depth compared to SABRE, demonstrating the practical value of coherence-guided compilation. This work establishes a scalable, hardware-aware approach that can generalize to future architectures where coherence becomes a central resource constraint in quantum compilation.

Abstract

Noisy intermediate-scale quantum (NISQ) devices impose dual challenges on quantum circuit execution: limited qubit connectivity requires extensive SWAP-gate routing, while time-dependent decoherence progressively degrades quantum information. Existing qubit mapping algorithms optimize for hardware topology and static calibration metrics but systematically neglect transverse relaxation dynamics (T2), creating a fundamental gap between compiler decisions and evolving noise characteristics. We present TRAM (Transverse Relaxation Time-Aware Qubit Mapping), a coherence-guided compilation framework that elevates decoherence mitigation to a primary optimization objective. TRAM integrates calibration-informed community detection to construct noise-resilient qubit partitions, generates time-weighted initial mappings that anticipate coherence decay, and dynamically schedules SWAP operations to minimize cumulative error accumulation. Evaluated on Qiskit-based simulators with realistic noise models, TRAM outperforms SABRE by 3.59% in fidelity, reduces gate count by 11.49%, and shortens circuit depth by 12.28%, establishing coherence-aware optimization as essential for practical quantum compilation in the NISQ era.

Figures (11)

• Figure 1: A quantum circuit and its corresponding DAG.
• Figure 2: A case of qubit allocation. The circles represent physical qubits, with the values inside each circle indicating the qubit’s transverse relaxation time $(T_2)$. The edges between the circles denote inter-qubit coupling relationships, and each edge is annotated with the corresponding two-qubit gate error. The value placed adjacent to each physical qubit represents its readout error. Qubits within the dashed box are the subset of physical qubits designated for allocation.
• Figure 3: Different routing processes for the same quantum operations. With respect to the $\texttt{qc.cx}(0,5)$ within the same quantum program, three routing schemes based on SWAP gates are designed to mediate interactions between the logical qubits $q_0$ and $q_5$. Specifically, the red, blue, and green lines in the figure delineate the SWAP gate paths employed in each respective scheme. $\text{Dist}[q_0][q_5]=2$ indicates that the number of SWAP gates required for each scheme is $2$.
• Figure 4: The quantum circuit of the decomposed SWAP gate.
• Figure 5: Qubit mapping by using CQTP in a nutshell. CQTP leverages hardware calibration data and the physical qubit coupling properties determined by the device topology to identify qualified schemes that comply with both the requirements of quantum programs and the physical qubit count.