Scenario-Aware Control of Segmented Ladder Bus: Design and FPGA Implementation

TL;DR

The paper tackles the challenge of energy-efficient interconnects for large-scale neuromorphic systems by introducing a scenario-aware control plane for the segmented ladder bus. It designs local controllers with preloaded scenario memories and presents two path-grouping algorithms—greedy and maximal-clique—to minimize switching states, with complexity analyses and FPGA-based validation. Results show the control plane consumes under 10% of network resources (average ~6.5%), and scalability analysis reveals the number of scenarios grows more slowly than network connectivity, with maximal-clique grouping yielding fewer scenarios than greedy. The work demonstrates a practical, scalable approach to manage dynamic segmentation in neuromorphic interconnects, enabling efficient deployment on large hardware.

Abstract

Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. The communication patterns in these systems are inherently sparse, asynchronous, and localized, as neural activity is characterized by temporal sparsity with occasional bursts of high traffic. These characteristics require optimized interconnects to handle high-activity bursts while consuming minimal power during idle periods. Among the proposed interconnect solutions, the dynamic segmented bus has gained attention due to its structural simplicity, scalability, and energy efficiency. Since the benefits of a dynamic segmented bus stem from its simplicity, it is essential to develop a streamlined control plane that can scale efficiently with the network. In this paper, we present a design methodology for a scenario-aware control plane tailored to a segmented ladder bus, with the aim of minimizing control overhead and optimizing energy and area utilization. We evaluated our approach using a combination of FPGA implementation and software simulation to assess scalability. The results demonstrated that our design process effectively reduces the control plane's area footprint compared to the data plane while maintaining scalability with network size.

Figures (5)

• Figure 1: Segmented ladder bus example with a switch controller.
• Figure 2: Mapping and scheduling design flow.
• Figure 3: Controller hardware design.
• Figure 4: Number of connections and scenarios scaling.
• Figure 5: Scenario scaling for different algorithms.