Selective Shuttling of Electrons on Helium Using a CMOS Control Platform

TL;DR

This work tackles the challenge of scalable qubit interconnects by integrating electrons on liquid helium with a CMOS control platform. It presents a 2D shuttling network across 128 transport channels and 96 packet sensors, with CCD-style clocking enabling deterministic transport of electron packets. The study provides evidence for single-electron packet initialization and demonstrates selective shuttling through 128 addressable columns, including the ability to merge and split packets for potential two-qubit operations. The results establish a promising, high-coherence, all-CMOS-compatible platform for large-scale quantum processors with all-to-all connectivity in a 2D architecture, suitable for surface-code implementations.

Abstract

Electrons bound to the surface of liquid helium are an emerging quantum computing platform, offering the potential for highly mobile spin qubits that can be manipulated using CMOS-fabricated devices. Here, as a step toward realizing this technology, we demonstrate selective two-dimensional shuttling of electrons across a helium film condensed on the surface of a CMOS control chip. The electrons are moved in packets containing, on average, several tens down to single electrons. We perform CCD-style electron shuttling in any of 128 transport microchannels, each of which links electron storage zones and sensing zones in the 2D plane. Shuttling sequences can be repeated at least 10$^9$ times with no detectable electron loss. The device serves as a prototype quantum information processing platform that is readily scalable to control large monolithically integrated arrays of single electron spins.

Figures (6)

• Figure 1: Schematic of the Wonder Lake Device showing surface microchannels and cross section. The surface-state electrons and superfluid helium occupy the channels defined in the uppermost layers of the aluminum interconnects. The channel walls are comprised of 505 nm of silicon oxide and 1.26 $\mu$m of aluminum. The CCD and control electrodes (visible on the right) are patterned on the second aluminum layer from the top. The lower interconnect layers are used for signal routing and shielding.
• Figure 2: Top-down view of the Wonder Lake device. In the center is an overview of the entire device area. the three large area reservoir electrodes are outlined in black dashed lines. In the four corners are SEM images of (clockwise, from top left) the Reservoir region and its CCD channels, the electron Shuttling Zone and its embedded packet sensors, the transition between the Reservoir region and electron Shuttling Zone, and the electron packet sensors to the left of the Reservoir.
• Figure 3: Electron packet initialization. (a) SEM image of the CCD array crossing the Reservoir. Wiring of the three phases to the CCD gates and the Door electrodes is shown via the orange, blue, green, and red wires respectively. The 3-phase voltage pulse sequence applied to the CCD gate lines to move electron packets in the positive $x$ direction is shown on the left as a function of time $t$. (b) The simulated potential energy surface during packet initialization. Here the electrodes are biased such that there are isolated minima atop each of the C phase gates on the CCD array. The Door gates for this simulation are in the "closed" state (-5V) such that the minima are separated from the reservoir. (c) Line cuts along $x=0$ of the potential energy profile in (b). The upper (lower) panel shows the potential as a black line when the Door gate is in the open (closed) state biased to $+2V$ ($-5V$). The measured electrochemical potential of electrons in the Reservoir $\phi_\mathrm{e}$ is shown with a red line.
• Figure 4: Electron sensor characterization. (a) Schematic of 1 of the 34 packet sensors which populate the left edge of the Reservoir. (b) Schematic of 1 of the 3264 packet sensors which populate the Shuttling Zone. In both cases, the packet sensor consists of a Drive gate, Barrier gate, Sense gate, and two Confinement gates, as described in the main text. (c) Schematic of the charge measurement scheme. Bias tees on the Drive and Barrier electrode allow for the driving and cancellation signals to be superimposed on the applied dc potential. The HEMT amplification circuitry wired to the sense gate amplifies the ac voltage established across the parasitic capacitance to ground, $C_\mathrm{P}$. (d) Experimental and simulated ac sensor voltage $V_\mathrm{O}$, for varying Barrier and Confinement electrode bias and 37 electrons loaded into the sensor. (e) Simulation results showing electron positions for the 37-electron packet for six different dc voltage configurations. The voltage configurations are indicated by the dots in the right panel of (d). The red and blue dots correspond to electron positions with the drive at its most positive (red) and negative (blue) values. The amplitude of the output signal, $V_\mathrm{O}$, is proportional to the number of electrons moving on and off the the sense electrode per cycle.
• Figure 5: Controlling the number of electrons per packet. (a) Measured $V_\mathrm{O}$ for varying Barrier ($V_\mathrm{B}$) and Confining ($V_\mathrm{C}$) voltages, following the same method as in Fig. \ref{['fig:SensorExplanation']}. Panels left to right show measured data for decreasing electron packet size. The solid lines are simulated current onset boundaries for $N_\mathrm{e}=11, 7, 2$ and $1$ as indicated in the boxes. (b) Cut-throughs of the data shown in (a) taken at $V_\mathrm{C}$ = -8, -6, -4 and -2 V (left to right). These voltage values are indicated by the dashed lines in (a). Also shown in black are data recorded for the case in which all electrons are ejected from the packet sensor. The solid lines are simulation results for $N_\mathrm{e}=11, 7, 2, 1$ and 0.