Cyclone: Designing Efficient and Highly Parallel QCCD Architectural Codesigns for Fault Tolerant Quantum Memory

TL;DR

The paper addresses the challenge of fault-tolerant quantum memory with non-topological CSS codes (e.g., Hypergraph Product and Bivariate Bicycle codes) on trapped-ion QCCD architectures. It introduces Cyclone, a roadblock-free, ring-based codesign where ancilla propagate in lockstep, achieving large parallelism, reduced depth, and improved logical error rates compared to grid-based baselines. The work combines hardware-software co-design, realistic noise models, and a specialized simulator (QCCDSim) to demonstrate up to ~$4\times$ speedups, ~$2$–$3\times$ reductions in logical error rate, and up to ~$20\times$ spacetime savings, with details on topology, scheduling, and resource costs. The results suggest Cyclone as a scalable, practical path toward dense, high-rate quantum memories in trapped-ion platforms, with potential extensions to related platforms like silicon quantum dots.

Abstract

Modular trapped-ion quantum computing hardware, known as QCCDs require shuttling operations in order to maintain effective all-to-all connectivity. Each module or trap can perform only one operation at a time, resulting in low intra-trap parallelism, but there is no restriction on operations happening on independent traps, enabling high inter-trap parallelism. Unlike their superconducting counterparts, the design space for QCCDs is relatively flexible and can be explored beyond current grid designs. In particular, current grid-based architectures significantly limit the performance of many promising, high-rate codes such as HGP codes and BB codes, suffering from numerous trap to trap ``roadblocks", forcing serialization and destroying the inherent parallelism of these codes.. Many of these codes are highly parallelizable, meaning that with appropriate hardware layouts and matching software schedules, execution latency can be reduced. Faster execution, in turn, reduces error accumulation from decoherence and heating, ultimately improving code performance when mapped to realistic hardware. To address this, we propose Cyclone, a circular software-hardware codesign that departs from traditional 2D grids in favor of a flexible ring topology, where ancilla qubits move in lockstep. Cyclone eliminates roadblocks, bounds total movement, and enables high levels of parallelism, resulting in up to ~4$\times$ speedup in execution times. With HGP codes, Cyclone achieves up to a 2$\times$ order of magnitude improvement in logical error rate, and with BB codes, this improvement reaches up to a 3$\times$ in order of magnitude.Spatially, Cyclone reduces the number of required traps and ancilla qubits by $2\times$.The overall spacetime improvement over a standard grid is up to $\sim 20 \times$, demonstrating Cyclone as a scalable and efficient alternative to conventional 2D QCCD architectures.

Figures (22)

• Figure 1: Left: the baseline grid architectural codesign is shown. This leads to gridlock, and large amounts of serialization on large arbitrary QEC codes with possible long-distance connections (non-topological codes). This design has both high spatial and temporal overhead. Middle: a mesh junction network is shown, which has high spatial requirements for junctions and bad temporal efficiency due to junction crossing overhead. Right: a symmetric roadblock-free design is shown. This design has low spatial and temporal overhead, with low control overhead due to its simplicity.
• Figure 2: From left to right and top to bottom, qubit labelling follows the ordering (trap number, ion number). The yellow qubits are to interact in this piece of the circuit. The ancilla bits (now moving and highlighted in green) are shuttled towards a junction in one step, across the junction, and then are merged into the target data trap. This process, along with the ensuing gates, is performed in parallel, and the new circuit is shown (X denotes a shuttling operation).
• Figure 3: Comparing Speedup of fully parallel vs. fully serial designs for the two classes of codes considered in this paper. Bars show a relative speedup ($\times$ times) over a fully serialized version of the code.
• Figure 4: We compare the 3 different grid inspired codesigns used in this paper a) The dynamic schedule on a grid, which we find performs worse than the baseline due to heavy roadblocking b) a static EJF schedule with a greedy cluster mapping on a grid, the baseline murali c) an alternative version of a grid with alternating horizontal/vertical meshes and L-shaped junctions.
• Figure 5: Comparing the logical error rate improvement upon speeding up the Baseline across different HGP codes. Physical error rate is held constant at $p = 5 \times 10^{-4}$. For all of these HGP codes, the baseline puts the code above the threshold.