Depth Optimization of Ansatz Circuits for Variational Quantum Algorithms

TL;DR

The paper tackles the depth limitations of variational quantum algorithms by replacing unitary CX gates with measurement-based, non-unitary equivalents that use an auxiliary qubit, mid-circuit measurements, and classical control. This approach, related to gate teleportation, enables shallower circuit depth at the expense of increased width and active volume, and is demonstrated on Burgers' equation dynamics to show faithful representation of both laminar and turbulent flows. Across a Pauli-twirled noise model, non-unitary cores exhibit fidelity advantages in regimes where idle noise dominates or CX errors are relatively small, highlighting regime-dependent trade-offs. The results suggest a practical path to scalable, near-term VQA implementations on ladder-type circuit architectures by trading depth for width and measurement overhead, with broad applicability to structured quantum circuits.

Abstract

The increasing depth of quantum circuits presents a major limitation for the execution of quantum algorithms, as the limited coherence time of physical qubits leads to noise that manifests as errors during computation. In this work, we focus on circuits relevant to variational quantum algorithms and demonstrate that their depth can be reduced by introducing additional qubits, mid-circuit measurements, and classically controlled operations. As an illustrative example, we consider nonlinear dynamics governed by the one-dimensional Burgers' equation, which has broad applications in computational fluid dynamics. In particular, we show that the proposed non-unitary quantum circuits can efficiently represent fluid flow configurations in both laminar and turbulent regimes. Furthermore, we demonstrate that, when noise is taken into account, these circuits are advantageous in regimes where two-qubit gate error rates are relatively low compared to idling error rates.

Figures (7)

• Figure 1: Generic ansatz circuit used in VQAs. The circuit consists of multiple layers, each starting with a random rotation on each qubit and a core circuit where two qubit gates can be added in different formations. At the end, another layer of rotations is added.
• Figure 2: In panel (a) three core circuits are depicted in a unitary (top) and a non-unitary (bottom) structure. The circuits provide an equivalent transformation on the register qubits. In panel (b) the measurement-based CX gate is depicted in two equivalent ways, which helps depending on the type of circuit that is under investigation.
• Figure 3: Simulation of three time-evolved states corresponding to the one-dimensional Burgers' equation using four qubits. The x-axis corresponds to the amplitude index, where index 0 represents the amplitude of $\ket{0000}$, index 1 represents the amplitude of $\ket{0001}$, and so on, while the y-axis corresponds to the amplitude value. State 1 is the time-evolved Gaussian state ($t = 0.083$) with kinematic viscosity coefficient set to the laminar flow regime ($\nu = 10$). State 2 is the time-evolved Gaussian state ($t = 0.83$) with kinematic viscosity coefficient set to the turbulent flow regime ($\nu = 10^{-3}$). State 3 is the time-evolved sinusoidal ($t = 0.83$) with kinematic viscosity coefficient set to the turbulent flow regime ($\nu = 10^{-3}$). An ansatz circuit based on non-unitary core circuit 1 was used for all simulated states with five layers. The infidelities reached for each state were 1.5e-13, 2.1e-13, and 5.2-14, respectively from left to right.
• Figure 4: In panel (a) two plots are presented for the unitary and the non-unitary version of core 1. Both have the same range in terms of idling error probability and CX error probability: 1e-5 to 1e-3 and 1e-4 to 1e-2, respectively. The colorbar corresponds to both plots and indicates the lower bound of process fidelity of the entire circuit, which appears to be at its highest for the unitary circuit when idling error probability is low, and for the non-unitary circuit when CX error probability is low. In panel (b) the difference of the process fidelities is shown, $\Delta$ Fidelity, where positive (red) indicates an advantage for the unitary circuit and negative (blue) for the non-unitary one. Finally, in panel (c) we present the $\Delta$ Fidelity against the number of register qubits for nine different error probabilities, which are also indicated as colored dots on the plot of panel (b).
• Figure 5: Step by step transition from a unitary to a non-unitary circuit. Step 0 is the initial unitary circuit. Step 1 shows the first substitution of a CX gate with its measurement-based equivalent. In step 2 the commutation of the conditional gate takes place. In step 3 the second substitution of CX is shown. Finally, in step 4 the last gate commutation takes place.