Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT

TL;DR

This work introduces VeriBToT, a Backtrack Tree of Thought framework for automated RTL Verilog generation that melds Top-down design with Design-for-Verification to enable self-decoupling of submodules and self-verification of intermediate designs. Five operators orchestrate a DFS-style reasoning process that partitions complex RTL into verifiable submodules and backtracks when verification reveals issues, improving both syntactic and functional correctness over traditional CoT approaches. Empirical results on open NL2V benchmarks show notable gains for general-purpose LLMs like ChatGPT-4 and DeepSeek-Coder-V2, with ablations confirming the necessity of self-verification and backtracking. The methodology demonstrates reduced debugging complexity and controlled token costs, suggesting VeriBToT as a broadly applicable paradigm for reliable, scalable automated hardware design using LLMs.

Abstract

Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog. However, challenges remain in ensuring the quality of Verilog generation. Complex designs often fail in a single generation due to the lack of targeted decoupling strategies, and evaluating the correctness of decoupled sub-tasks remains difficult. While the chain-of-thought (CoT) method is commonly used to improve LLM reasoning, it has been largely ineffective in automating IC design workflows, requiring manual intervention. The key issue is controlling CoT reasoning direction and step granularity, which do not align with expert RTL design knowledge. This paper introduces VeriBToT, a specialized LLM reasoning paradigm for automated Verilog generation. By integrating Top-down and design-for-verification (DFV) approaches, VeriBToT achieves self-decoupling and self-verification of intermediate steps, constructing a Backtrack Tree of Thought with formal operators. Compared to traditional CoT paradigms, our approach enhances Verilog generation while optimizing token costs through flexible modularity, hierarchy, and reusability.

Figures (7)

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• Figure 5: The comparison between traditional CoT paradigms.
• Figure 6: The motivation of VeriBToT: each node in the diagram represents a thought step, which is limited to a module within the hierarchical RTL design (including natural language descriptions, RTL design Verilog, and testbench Verilog).