Physics-Constrained Adaptive Neural Networks Enable Real-Time Semiconductor Manufacturing Optimization with Minimal Training Data

TL;DR

This work tackles the EUV lithography optimization bottleneck by introducing physics-constrained adaptive learning, which jointly tunes learnable electromagnetic parameters to achieve sub-nanometer Edge Placement Error (EPE) with minimal training data. A differentiable forward model combines Fresnel diffraction, absorption, optical blur, phase shift, and contrast modulation, guided by a CNN generator and an adaptive physics simulator to enable cross-geometry generalization across 18 pattern types. The approach delivers data-efficient learning, achieving sub-nm EPE on a majority of patterns (with substantial speedups over rigorous EM solvers) and demonstrates the practicality of physics-informed deployment for real-time manufacturing optimization. These results suggest a scalable, sustainable pathway to industrial lithography optimization and broader physics-constrained manufacturing applications, reducing computational cost while maintaining manufacturing precision.

Abstract

The semiconductor industry faces a computational crisis in extreme ultraviolet (EUV) lithography optimization, where traditional methods consume billions of CPU hours while failing to achieve sub-nanometer precision. We present a physics-constrained adaptive learning framework that automatically calibrates electromagnetic approximations through learnable parameters $\boldsymbolθ = \{θ_d, θ_a, θ_b, θ_p, θ_c\}$ while simultaneously minimizing Edge Placement Error (EPE) between simulated aerial images and target photomasks. The framework integrates differentiable modules for Fresnel diffraction, material absorption, optical point spread function blur, phase-shift effects, and contrast modulation with direct geometric pattern matching objectives, enabling cross-geometry generalization with minimal training data. Through physics-constrained learning on 15 representative patterns spanning current production to future research nodes, we demonstrate consistent sub-nanometer EPE performance (0.664-2.536 nm range) using only 50 training samples per pattern. Adaptive physics learning achieves an average improvement of 69.9\% over CNN baselines without physics constraints, with a significant inference speedup over rigorous electromagnetic solvers after training completion. This approach requires 90\% fewer training samples through cross-geometry generalization compared to pattern-specific CNN training approaches. This work establishes physics-constrained adaptive learning as a foundational methodology for real-time semiconductor manufacturing optimization, addressing the critical gap between academic physics-informed neural networks and industrial deployment requirements through joint physics calibration and manufacturing precision objectives.

Figures (21)

• Figure 1: Physics parameter adaptation across pattern families in EUV lithography optimization. Physics-constrained adaptive learning automatically calibrates five electromagnetic parameters $\boldsymbol{\theta} = \{\theta_d, \theta_a, \theta_b, \theta_p, \theta_c\}$ across semiconductor patterns within 500 epochs. Diffraction parameter ($\theta_d$) ranges from 0.250 (logic gates) to 0.440 (3 nm FinFET), with red intensities indicating diffraction strength. Absorption coefficient ($\theta_a$) varies from 0.032 (High-NA contacts) to 0.150 (FinFET, STI), with blue intensities representing material attenuation. Optical blur ($\theta_b$) shows largest variation from 3.80 nm (contacts, memory) to 21.78 nm (line-space patterns), with green intensities indicating spatial resolution requirements. Contrast factor ($\theta_c$) ranges from 0.649 (logic gates) to 1.762 (FinFET), with purple intensities representing resist nonlinearity.
• Figure 2: Comprehensive EUV lithography pattern library for physics-constrained learning validation. Systematically generated masking patterns spanning production through research technologies, rendered at 6.328 nm pixel resolution across 810 nm fields. Colored labels indicate difficulty: green (Easy, 70-90% success), orange (Moderate, 40-70% success), red (Hard, 10-40% success). (a), Logic gates with H-shaped interconnects (9.9% fill, 31.6 nm features). (b), EUV line-space: 16 nm lines, 32 nm pitch (58.2% fill, 19.0 nm features). (c), EUV contacts: 40 nm contacts, 50 nm pitch (56.2% fill, 38.0 nm features). (d), EUV metal: 24 nm lines, 42 nm pitch (68.1% fill, 19.0 nm features). (e), Shallow trench isolation (74.2% fill, 120.2 nm features). (f), 3nm FinFET: 12 nm fins, 24 nm pitch (52.3% fill, 12.7 nm features). (g), DRAM arrays: 30×50 nm cells (71.8% fill, 31.6 nm features). (h), SRAM cells with six-transistor structure (52.4% fill, 12.7 nm features). (i), Random contact cuts at 70% density (27.3% fill, 50.6 nm features). (j), High-NA lines: 12 nm features, 24 nm pitch (50.0% fill, 12.7 nm features). (k), High-NA contacts for 0.55 NA systems (43.1% fill, 25.3 nm features). (l), Curvilinear patterns with sub-wavelength curved features (8.7% fill, 6.3 nm features). Blue regions indicate material presence, white regions represent etched areas. Patterns progress from manufacturable through challenging to research-phase difficulty, providing comprehensive training data across EUV manufacturing capabilities.
• Figure 3: Advanced EUV lithography patterns for next-generation semiconductor manufacturing. Computationally generated masking patterns representing critical challenges across two development tiers: Tier 1 (green labels) for 2024-2025 production and Tier 3 (red labels) for 2027-2030 research. All patterns span 810 nm field with 6.328 nm pixel resolution. (a),(b), GAAFET nanosheets with vertically stacked channels: 3-sheet (12 nm width) and 2-sheet (15 nm width) variants for 3 nm nodes. (c),(d), MBCFET patterns with bridge connections between variable-width nanosheets (8-20 nm range) for current optimization. (e),(f), Backside power delivery featuring buried rails and nano through-silicon vias: standard (20 nm rails, 15 nm vias) and dense (15 nm rails, 12 nm vias) configurations for 2 nm nodes. (g),(h), CFET with vertically stacked n-type and p-type devices: basic (5 nm isolation) and tight-pitch (3 nm isolation, 8 nm channels) for sub-1.4 nm scaling. (i),(j), High-NA EUV patterns incorporating anamorphic effects: 8 nm features with 16 nm pitch (2× distortion) and 6 nm features (2.5× distortion) for 0.55 NA systems. (k),(l), Strain engineering with silicon-germanium regions: compressive (25 nm features, 40 nm spacing) and tensile (30 nm features, 50 nm spacing) stress patterns. Blue regions indicate material presence, white regions represent etched areas. Expected success rates: 40-70% (Tier 1) and 10-40% (Tier 3).
• Figure 4: Physics-constrained learning performance across EUV lithography patterns within 500-epoch budget. Cross-geometry learning evaluation across 11 semiconductor masking patterns, measuring EPE relative to 1 nm target precision and 4.5 nm baseline accuracy. (a), Final EPE performance by pattern type. Eight patterns achieve sub-nanometer precision (light blue bars: logic gates, EUV contacts, EUV metal, FinFET, DRAM arrays, SRAM cells, High-NA contacts, High-NA curvilinear), while three exceed target (colored bars: EUV line-space, STI pattern, contact cuts, High-NA lines). Green dashed line shows 1 nm target, red dashed line shows 4.5 nm baseline. (b), Performance improvement percentages relative to baseline corresponding to CNN, ranging from 40.6% (logic gates) to 93.1% (DRAM arrays). Most patterns achieve 80-90% improvement. Colors correspond to panel (a) pattern types. (c), Best achieved EPE during training (light blue bars) versus final convergence EPE (orange bars) on a logarithmic scale. Minimal degradation indicates stable convergence across pattern types. (d), Training efficiency: final EPE plotted against training samples required (48-52 patterns). Circle colors indicate improvement percentage from panel (b) (purple: 40-50%, yellow: 90-95%). Lower-left positions represent optimal efficiency. Results demonstrate sub-nanometer precision achievable across diverse pattern geometries within practical computational constraints, with performance strongly dependent on pattern complexity rather than training duration.
• Figure 5: Physics-constrained adaptive learning achieves 5.373 nm edge placement error on contact array pattern within 500-epoch computational budget. Physics-constrained learning analysis demonstrates intermediate performance on semiconductor contact array with learned electromagnetic parameters: diffraction strength 0.250, absorption coefficient 0.054, optical blur 3.8 nm, phase shift 0.000 rad, contrast factor 0.820. (a), Target binary contact pattern showing regular array of square features with black regions representing opaque photomask areas and white regions indicating transparent contact openings. (b), Generated photomask displaying preserved contact geometry through continuous grayscale transmission values that maintain spatial periodicity while enabling gradient-based optimization. (c), Physics-simulated aerial image rendered in dark red colormap showing optical effects on contact features with moderate blurring but recognizable periodic structure (intensity scale maximum 5.37). (d), Absolute difference map revealing distributed prediction errors in light red intensities across the pattern area. (e), Horizontal cross-section comparison displaying target pattern (blue line) with sharp binary contact edges versus simulated intensity profile (red line) exhibiting optical smoothing effects characteristic of diffraction-limited imaging. (f), Learned physics parameters represented as colored bars: diffraction (red), absorption (blue), blur in nanometers (green), phase in radians (gray), contrast modulation (purple). (g), EPE performance comparison showing current result (orange bar, 5.37 nm) exceeding 1.00 nm target precision (yellow) but achieving better performance than 4.50 nm baseline (blue). (h), Intensity distribution histograms comparing sharp target distribution (blue) concentrated at binary extremes versus simulated distribution (red) showing intermediate values with preserved bimodal characteristics. Results demonstrate physics-constrained learning capability for contact pattern optimization while highlighting resolution challenges for sub-nanometer precision requirements in advanced semiconductor manufacturing.